Random Number Generation Based on Cryptocurrency Prices and Linear Feedback Shift Register - Ayumu Chiba; Shuichi Ichikawa (Twelfth International Symposium on Computing and Networking, CANDAR 2024, Naha, Japan, November 26-29, 2024, 2024)

Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator - Naoki Fujieda; Shuichi Ichikawa; Ryusei Oya; Hitomi Kishibe (IEICE Trans. Inf. Syst., 2023)

Pseudo-Random Number Generation by Staggered Sampling of LFSR - Shuichi Ichikawa (Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28 - Dec. 1, 2023, 2023)

An HLS implementation of on-the-fly randomness test for TRNGs - Ryusei Oya; Naoki Fujieda; Shuichi Ichikawa (Tenth International Symposium on Computing and Networking, CANDAR 2022, Himeji, Japan, November 21-24, 2022, 2022)

A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC) - Shunsuke Matsuoka; Shuichi Ichikawa; Naoki Fujieda (Int. J. Circuit Theory Appl., 2021)

An Analysis of DCM-Based True Random Number Generator - Naoki Fujieda; Masaaki Takeda; Shuichi Ichikawa (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Netlist-based Measures for Hardware Obfuscation: A Preliminary Study - Shotaro Yamada; Shuichi Ichikawa (Eighth International Symposium on Computing and Networking Workshops, CANDAR 2020 Workshops, Naha, Japan, November 24-27, 2020, 2020)

A light-weight implementation of latch-based true random number generator - Naoki Fujieda; Hitomi Kishibe; Shuichi Ichikawa (15th International Wireless Communications & Mobile Computing Conference, IWCMC 2019, Tangier, Morocco, June 24-28, 2019, 2019)

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs - Naoki Fujieda; Shuichi Ichikawa (IEICE Electron. Express, 2018)

Evaluation of Register Number Abstraction for Enhanced Instruction Register Files - Naoki Fujieda; Kiyohiro Sato; Ryodai Iwamoto; Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2018)

An Analysis on Randomness of Path ORAM for Light-Weight Implementation - Hiroki Fujita; Naoki Fujieda; Shuichi Ichikawa (Sixth International Symposium on Computing and Networking, CANDAR Workshops 2018, Takayama, Japan, November 27-30, 2018, 2018)

A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity - Naoki Fujieda; Yusuke Ayuzawa; Masato Hongo; Shuichi Ichikawa (TENCON 2018 - 2018 IEEE Region 10 Conference, Jeju, South Korea, October 28-31, 2018, 2018)

A Virtual Cache for Overlapped Memory Accesses of Path ORAM - Naoki Fujieda; Ryo Yamauchi; Hiroki Fujita; Shuichi Ichikawa (Int. J. Netw. Comput., 2017)

An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis - Yoshiki Ishigaki; Naoki Fujieda; Yuumi Matsuoka; Kazuki Uyama; Shuichi Ichikawa (Fifth International Symposium on Computing and Networking, CANDAR 2017, Aomori, Japan, November 19-22, 2017, 2017)

A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration - Seiya Ogido; Chikatoshi Yamada; Kei Miyagi; Shuichi Ichikawa (Fifth International Symposium on Computing and Networking, CANDAR 2017, Aomori, Japan, November 19-22, 2017, 2017)

Evaluation of the hardwired sequence control system generated by high-level synthesis - Naoki Fujieda; Shuichi Ichikawa; Yoshiki Ishigaki; Tasuku Tanaka (26th IEEE International Symposium on Industrial Electronics, ISIE 2017, Edinburgh, United Kingdom, June 19-21, 2017, 2017)

Design and implementation of instruction indirection for embedded software obfuscation - Naoki Fujieda; Tasuku Tanaka; Shuichi Ichikawa (Microprocess. Microsystems, 2016)

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM - Naoki Fujieda; Ryo Yamauchi; Shuichi Ichikawa (Fourth International Symposium on Computing and Networking, CANDAR 2016, Hiroshima, Japan, November 22-25, 2016, 2016)

A Complement to Enhanced Instruction Register File against Embedded Software Falsification - Naoki Fujieda; Kiyohiro Sato; Shuichi Ichikawa (Proceedings of the 5th Program Protection and Reverse Engineering Workshop, PPREW@ACSAC, Los Angeles, CA, USA, December 8, 2015, 2015)

An XOR-Based Approach to Merging Entries for Instruction Register Files - Naoki Fujieda; Shuichi Ichikawa (The First International Symposium on Computing and Networking - Across Practical Development and Theoretical Research, Dogo SPA Resort, Matsuyama, Japan, December 4-6, 2013, 2013)

FPGA Implementation of Metastability-Based True Random Number Generator - Hisashi Hata; Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2012)

Reduction of Power Consumption in Key-specific AES Circuits - Shunsuke Matsuoka; Shuichi Ichikawa (Third International Conference on Networking and Computing, ICNC 2012, Okinawa, Japan, December 5-7, 2012, 2012)

Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning - Satoru Tamura; Chikatoshi Yamada; Shuichi Ichikawa (Third International Conference on Networking and Computing, ICNC 2012, Okinawa, Japan, December 5-7, 2012, 2012)

Foreword - Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2011)

Optimizing process allocation of parallel programs for heterogeneous clusters - Shuichi Ichikawa; Sho Takahashi; Yuu Kawai (Concurr. Comput. Pract. Exp., 2009)

Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study - Shuichi Ichikawa; Shoichiro Takagi (2009 International Conference on Complex, Intelligent and Software Intensive Systems, CISIS 2009, Fukuoka, Japan, March 16-19, 2009, 2009)

Diversification of Processors Based on Redundancy in Instruction Set - Shuichi Ichikawa; Takashi Sawada; Hisashi Hata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Redundancy in Instruction Sequences of Computer Programs - Kazuhiro Hattanda; Shuichi Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm - Ryoichiro Atono; Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2006)

Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937 - Shiro Konuma; Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2005)

Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation - Yoshinori Kishimoto; Shuichi Ichikawa (Parallel Comput., 2005)

The Evaluation of Davidson's Digital Signature Scheme - Kazuhiro Hattanda; Shuichi Ichikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004)

The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem - Shoji Yamamoto; Shuichi Ichikawa; Hiroshi Yamamoto (IEICE Trans. Inf. Syst., 2004)

An Execution-Time Estimation Model for Heterogeneous Clusters - Yoshinori Kishimoto; Shuichi Ichikawa (18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004)

Data Dependent Circuit Design: A Case Study - Shoji Yamamoto; Shuichi Ichikawa; Hiroshi Yamamoto (Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, 2003)

Data Dependent Circuit for Subgraph Isomorphism Problem - Shuichi Ichikawa; Shoji Yamamoto (Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, 2002)

Redundancy in 3D Polygon Models and Its Application to Digital Signature - Shuichi Ichikawa; H. Chiyama; K. Akabane (The 10-th International Conference in Central Europe on Computer Graphics, Visualization and Computer Vision'2002, WSCG 2002, University of West Bohemia, Campus Bory, Plzen-Bory, Czech Republic, February 4-8, 2002, 2002)

Hardware Accelerator for Subgraph Isomorphism Problems - Shuichi Ichikawa; Lerdtanaseangtham Udorn; Kouji Konishi (8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, 2000)

Evaluation of Accelerator Designs for Subgraph Isomorphism Problem - Shuichi Ichikawa; Hidemitsu Saito; Lerdtanaseangtham Udorn; Kouji Konishi (Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, 2000)

Evaluation of range-checking addressing modes and the architecture of FLATS2 - Shuichi Ichikawa; Mitsuhisa Sato; Eiichi Goto (Syst. Comput. Jpn., 1992)

Pseudorandom Rounding for Truncated Multipliers - Nobuaki Yoshida; Eiichi Goto; Shuichi Ichikawa (IEEE Trans. Computers, 1991)

Multiple instruction streams in a highly pipelined processor - Mitsuhisa Sato; Shuichi Ichikawa; Eiichi Goto (Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990, 1990)

CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines - Kentaro Shimizu; Eiichi Goto; Shuichi Ichikawa (IEEE Trans. Computers, 1989)

Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking - Mitsuhisa Sato; Shuichi Ichikawa; Eiichi Goto (Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, 1989)