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S. Ramesh 0002
Ramesh S. 0002 – Sethu Ramesh
Person information
- affiliation: General Motors R&D, India Science Lab, Bangalore, India
Other persons with the same name
- S. Ramesh (aka: Ramesh S.) — disambiguation page
- S. Ramesh 0001 — Indian Institute of Technology, Bombay, Mumbai, India
- S. Ramesh 0003
(aka: Ramesh Sekaran) — Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, India (and 2 more)
- S. Ramesh 0004 (aka: Shiva Ramesh 0004) — LSI Logic Corporation, Milpitas, CA, USA
- S. Ramesh 0005
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2020 – today
- 2024
- [c68]Amirhossein Zolfagharian
Safety Monitoring of Deep Reinforcement Learning Agents. ICSE Companion 2024: 286-287 - [c67]Nicholas Annable
Comprehensive Change Impact Analysis Applied to Advanced Automotive Systems. SAFECOMP 2024: 134-149 - [i9]Zohreh Aghababaeyan, Manel Abdellatif, Lionel C. Briand, S. Ramesh:
DiffGAN: A Test Generation Approach for Differential Testing of Deep Neural Networks. CoRR abs/2410.19794 (2024) - 2023
- [j22]Ramy Shahin
Applying declarative analysis to industrial automotive software product line models. Empir. Softw. Eng. 28(2): 40 (2023) - [j21]Zohreh Aghababaeyan
Black-Box Testing of Deep Neural Networks through Test Case Diversity. IEEE Trans. Software Eng. 49(5): 3182-3204 (2023) - [j20]Amirhossein Zolfagharian
A Search-Based Testing Approach for Deep Reinforcement Learning Agents. IEEE Trans. Software Eng. 49(7): 3715-3735 (2023) - [c66]Unmesh D. Bordoloi, Samarjit Chakraborty
Autonomy-driven Emerging Directions in Software-defined Vehicles. DATE 2023: 1-6 - [i8]Amirhossein Zolfagharian, Manel Abdellatif, Lionel C. Briand, Ramesh S.:
SMARLA: A Safety Monitoring Approach for Deep Reinforcement Learning Agents. CoRR abs/2308.02594 (2023) - [i7]Jian Chen, Manar H. Alalfi, Thomas R. Dean, Ramesh S.:
SimSched: A tool for Simulating Autosar Implementaion in Simulink. CoRR abs/2308.14974 (2023) - 2022
- [j19]Sofia Ananieva
A conceptual model for unifying variability in space and time: Rationale, validation, and illustrative applications. Empir. Softw. Eng. 27(5): 101 (2022) - [j18]Dnyanesh Rajpathak, Prakash Mohan Peranandam, S. Ramesh:
Automatic development of requirement linking matrix based on semantic similarity for robust software development. J. Syst. Softw. 186: 111211 (2022) - [i6]Amirhossein Zolfagharian, Manel Abdellatif
Search-Based Testing Approach for Deep Reinforcement Learning Agents. CoRR abs/2206.07813 (2022) - 2021
- [c65]Ramy Shahin, Robert Hackman, Rafael F. Toledo, S. Ramesh, Joanne M. Atlee, Marsha Chechik:
Applying Declarative Analysis to Software Product Line Models: An Industrial Study. MoDELS 2021: 145-155 - [i5]Ramy Shahin, Robert Hackman, Rafael F. Toledo, S. Ramesh, Joanne M. Atlee, Marsha Chechik:
Applying Declarative Analysis to Software Product Line Models: An Industrial Study. CoRR abs/2107.07690 (2021) - [i4]Zohreh Aghababaeyan, Manel Abdellatif, Lionel C. Briand, Ramesh S., Mojtaba Bagherzadeh:
Black-Box Testing of Deep Neural Networks through Test Case Diversity. CoRR abs/2112.12591 (2021) - 2020
- [c64]Sofia Ananieva, Sandra Greiner, Thomas Kühn, Jacob Krüger
A conceptual model for unifying variability in space and time. SPLC (A) 2020: 15:1-15:12
2010 – 2019
- 2019
- [j17]Omer Nguena Timo
Fault model-driven testing from FSM with symbolic inputs. Softw. Qual. J. 27(2): 501-527 (2019) - [j16]Joseph D'Ambrosio, Arun Adiththan, Edwin Ordoukhanian
An MBSE Approach for Development of Resilient Automated Automotive Systems. Syst. 7(1): 1 (2019) - [j15]Debiprasanna Sahoo
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24(2): 20:1-20:23 (2019) - [c63]Omer Nguena Timo, Alexandre Petrenko
Using Imprecise Test Oracles Modelled by FSM. ICST Workshops 2019: 32-39 - [c62]Sofia Ananieva, Timo Kehrer, Heiko Klare
Towards a conceptual model for unifying variability in space and time. SPLC (B) 2019: 67:1-67:5 - 2018
- [j14]Debiprasanna Sahoo
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2485-2496 (2018) - [c61]Jian Chen, Manar H. Alalfi
Modeling AUTOSAR Implementations in Simulink. ECMFA 2018: 279-292 - [c60]Omer Nguena-Timo, Alexandre Petrenko
Checking Sequence Generation for Symbolic Input/Output FSMs by Constraint Solving. ICTAC 2018: 354-375 - 2017
- [j13]Huafeng Yu, Stanley Bak, Xin Li, Corina S. Pasareanu, Ramesh S., Qi Zhu:
Guest Editorial. IET Cyper-Phys. Syst.: Theory & Appl. 2(2): 55-56 (2017) - [c59]S. Ramesh, Birgit Vogel-Heuser, Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty
Specification, Verification and Design of Evolving Automotive Software: Invited. DAC 2017: 83:1-83:6 - [c58]Arun Adiththan, Kaliappa Ravindran, S. Ramesh:
Management of QoS-oriented Adaptation in Automobile Cruise Control Systems. ICAC 2017: 79-80 - [c57]Omer Nguena-Timo
Multiple Mutation Testing from Finite State Machines with Symbolic Inputs. ICTSS 2017: 108-125 - [c56]Arun Adiththan, Kaliappa Ravindran, S. Ramesh:
Situation-Based Autonomic Management of Automobile Cruise Control Systems. FAS*W@SASO/ICCAC 2017: 103-108 - 2016
- [j12]Ganesh Khandu Narwane, José Angel Galindo
Traceability Analyses between Features and Assets in Software Product Lines. Entropy 18(8): 269 (2016) - [j11]Indranil Saha, Suman Roy
Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey. Proc. IEEE 104(5): 904-922 (2016) - [c55]Boris Madzar, Jalil Boudjadar, Juergen Dingel, Thomas E. Fuhrman, S. Ramesh:
Formal Analysis of Predictable Data Flow in Fault-Tolerant Multicore Systems. FACS 2016: 153-171 - [c54]Alexandre Petrenko
Multiple Mutation Testing from FSM. FORTE 2016: 222-238 - [c53]Sujit Kumar Chakrabarti
SymTest: A Framework for Symbolic Testing of Embedded Software. ISEC 2016: 48-58 - [c52]Paolo Giusto, Ramesh S., Sudhakaran M.:
Modeling and Analysis of Automotive Systems: Current Approaches and Future Trends. MODELSWARD 2016: 704-710 - [c51]Alexandre Petrenko
Test Generation by Constraint Solving and FSM Mutant Killing. ICTSS 2016: 36-51 - [c50]Anuradha Annaswamy, Samarjit Chakraborty, Dip Goswami, S. Ramesh, Marilyn Wolf:
Trustworthy Cyber Physical Systems. VLSID 2016: 19-20 - [c49]Samarjit Chakraborty, S. Ramesh:
Technologies for Safe and Intelligent Transportation Systems. VLSID 2016: 56-58 - 2015
- [j10]Kamalesh Ghosh, Pallab Dasgupta, S. Ramesh:
Automated Planning as an Early Verification Tool for Distributed Control. J. Autom. Reason. 54(1): 31-68 (2015) - [j9]Samarjit Chakraborty
Guest Editorial Special Section on Automotive Embedded Systems and Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1701-1703 (2015) - [c48]Shankara Narayanan Krishna, Ganesh Khandu Narwane, S. Ramesh, Ashutosh Trivedi
Compositional modeling and analysis of automotive feature product lines. DAC 2015: 57:1-57:6 - [c47]Alexandre Petrenko
Model-based testing of automotive software: some challenges and solutions. DAC 2015: 118:1-118:6 - [c46]Michalis Famelis, Levi Lucio, Gehan M. K. Selim, Alessio Di Sandro
Migrating Automotive Product Lines: A Case Study. ICMT 2015: 82-97 - [c45]Ramesh S.:
Automobile: Aircraft or smartphone? Modeling challenges and opportunities in Automotive Systems (keynote). MoDELS 2015: 3 - [c44]Guillaume Langelier, Arnaud Dury, Alexandre Petrenko
Building an interactive test development environment for cyclic executive systems. SIES 2015: 127-135 - [e1]Michal Antkiewicz, Joanne M. Atlee, Juergen Dingel, S. Ramesh:
Proceedings of the International Workshop on Modelling in Automotive Software Engineering co-located with ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS 2015), Ottawa, Canada. September 27, 2015. CEUR Workshop Proceedings 1487, CEUR-WS.org 2015 [contents] - 2014
- [j8]Albert Mo Kim Cheng
Guest Editorial: Special Issue on Rigorous Modeling and Analysis of Cyber-Physical Systems. IEEE Embed. Syst. Lett. 6(1): 2-3 (2014) - [j7]Manoj G. Dixit, S. Ramesh, Pallab Dasgupta:
Time-budgeting: a component based development methodology for real-time embedded systems. Formal Aspects Comput. 26(3): 591-621 (2014) - [j6]Swarup Mohalik, Ambar A. Gadkari, Anand Yeolekar, K. C. Shashidhar, S. Ramesh:
Automatic test case generation from Simulink/Stateflow models using model checking. Softw. Test. Verification Reliab. 24(2): 155-180 (2014) - [c43]Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh:
Translation Validation for Stateflow to C. DAC 2014: 23:1-23:6 - [c42]Kaliappa Ravindran, Sethu Ramesh:
Model-based design of cyber-physical software systems for smart worlds: a software engineering perspective. MoSEMInA 2014: 62-71 - [c41]Omer Nguena-Timo
Reachability in hierarchical machines. IRI 2014: 475-482 - [p1]Manoj G. Dixit, S. Ramesh, Pallab Dasgupta:
Early Time-Budgeting for Component-Based Embedded Control Systems. Embedded Systems Development, From Functional Models to Implementations 2014: 123-137 - 2013
- [j5]Jean-Vivien Millo, Frédéric Mallet
Scenario-based verification in presence of variability using a synchronous approach. Frontiers Comput. Sci. 7(5): 650-672 (2013) - [c40]Manoranjan Satpathy, S. Ramesh, Colin F. Snook
A mixed approach to rigorous development of control designs. CACSD 2013: 7-12 - [c39]Swarup Mohalik, Devesh B. Chokshi, Manoj G. Dixit, A. C. Rajeev, S. Ramesh:
Scalable model-checking for precise end-to-end latency computation. CACSD 2013: 19-24 - [c38]Dip Goswami, Martin Lukasiewycz, Matthias Kauer, Sebastian Steinhorst
Model-based development and verification of control software for electric vehicles. DAC 2013: 96:1-96:9 - [c37]Alexandre Petrenko
A Method and Tool for Test Optimization for Automotive Controllers. ICST Workshops 2013: 198-207 - [c36]Jean-Vivien Millo, S. Ramesh, Shankara Narayanan Krishna, Ganesh Khandu Narwane:
Compositional Verification of Software Product Lines. IFM 2013: 109-123 - [c35]Manoranjan Satpathy, Colin F. Snook, Silky Arora, S. Ramesh, Michael J. Butler:
Systematic Development of Control Designs via Formal Refinement. MODELSWARD 2013: 143-148 - 2012
- [j4]Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan:
A dynamic assertion-based verification platform for validation of UML designs. ACM SIGSOFT Softw. Eng. Notes 37(1): 1-14 (2012) - [j3]Manoranjan Satpathy, Anand Yeolekar, Prakash Mohan Peranandam, S. Ramesh:
Efficient coverage of parallel and hierarchical stateflow models for test case generation. Softw. Test. Verification Reliab. 22(7): 457-479 (2012) - [c34]Jean-Vivien Millo, S. Ramesh:
Relating Requirement and Design Variabilities. APSEC Workshops 2012: 35-42 - [c33]Kamalesh Ghosh, Pallab Dasgupta, S. Ramesh:
Planning with Action Prioritization and New Benchmarks for Classical Planning. Australasian Conference on Artificial Intelligence 2012: 779-790 - [c32]A. C. Rajeev, Swarup Mohalik, S. Ramesh:
Verifying timing synchronization constraints in distributed embedded architectures. DATE 2012: 200-205 - [c31]Prakash Mohan Peranandam, Sachin Raviram, Manoranjan Satpathy, Anand Yeolekar, Ambar A. Gadkari, S. Ramesh:
An integrated test generation tool for enhanced coverage of Simulink/Stateflow models. DATE 2012: 308-311 - [c30]Sachin Raviram, Prakash Mohan Peranandam, Manoranjan Satpathy, S. Ramesh:
SmartTestGen+: A Test Suite Booster for Enhanced Structural Coverage. ICTAC 2012: 164-167 - [c29]Silky Arora, Prahladavaradan Sampath, S. Ramesh:
Resolving uncertainty in automotive feature interactions. RE 2012: 21-30 - [c28]Swarup Mohalik, S. Ramesh, Jean-Vivien Millo, Shankara Narayanan Krishna, Ganesh Khandu Narwane:
Tracing SPLs precisely and efficiently. SPLC (1) 2012: 186-195 - [i3]Shankara Narayanan Krishna, Ganesh Khandu Narwane, S. Ramesh, Swarup Mohalik, Jean-Vivien Millo:
Formalizing Traceability and Derivability in Software Product Lines. CoRR abs/1201.0595 (2012) - [i2]Jean-Vivien Millo, S. Ramesh, Shankara Narayanan Krishna, Ganesh Khandu Narwane:
Compositional Verification of Evolving Software Product Lines. CoRR abs/1212.4258 (2012) - 2011
- [j2]Silky Arora, Ambar A. Gadkari, S. Ramesh:
Scenario-Based Specification of Automotive Requirements With Quantitative Constraints and Synthesis of SL/SF Monitors. IEEE Embed. Syst. Lett. 3(2): 62-65 (2011) - [j1]Manoj G. Dixit, S. Ramesh, Pallab Dasgupta:
Some results on Parametric Temporal Logic. Inf. Process. Lett. 111(20): 994-998 (2011) - [c27]S. Ramesh, Ambar A. Gadkari:
Rigorous model-based design & verification flow for in-vehicle software. DAC 2011: 13-16 - [c26]Sumit Kumar Jha, Christopher James Langmead
When to stop verification?: Statistical trade-off between expected loss and simulation cost. DATE 2011: 1309-1314 - [c25]Manfred Broy, Samarjit Chakraborty
Cross-layer analysis, testing and verification of automotive control software. EMSOFT 2011: 263-272 - [c24]Jean-Vivien Millo, Swarup Mohalik, S. Ramesh:
Integrated analysis of software product lines: a constraint based framework for consistency, liveness, and commonness checking. ISEC 2011: 41-50 - [c23]Prahladavaradan Sampath, Silky Arora, S. Ramesh:
Evolving specifications formally. RE 2011: 5-14 - 2010
- [c22]Manoj G. Dixit, Pallab Dasgupta, S. Ramesh:
Taming the component timing: A CBD methodology for real-time embedded systems. DATE 2010: 1649-1652 - [c21]A. C. Rajeev, Swarup Mohalik, Manoj G. Dixit, Devesh B. Chokshi, S. Ramesh:
Schedulability and end-to-end latency in distributed ECU networks: formal modeling and precise estimation. EMSOFT 2010: 129-138 - [c20]Samarjit Chakraborty
Model-based analysis, synthesis and testing of automotive hardware/software architectures. EMSOFT 2010: 299-300 - [c19]A. C. Rajeev, Prahladavaradan Sampath, K. C. Shashidhar, S. Ramesh:
CoGenTe: a tool for code generator testing. ASE 2010: 349-350
2000 – 2009
- 2009
- [c18]Deepak D'Souza, Madhu Gopinathan, S. Ramesh, Prahladavaradan Sampath:
Supervisory control for real-time systems based on conflict-tolerant controllers. CASE 2009: 555-560 - [c17]Aditya Kanade, Rajeev Alur, Franjo Ivancic, S. Ramesh, Sriram Sankaranarayanan, K. C. Shashidhar:
Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models. CAV 2009: 430-445 - 2008
- [c16]S. Xu, Ratnesh Kumar, Shengbing Jiang, S. Ramesh:
A simulation condition for correct asynchronous implementation of synchronous design. ACC 2008: 1728-1733 - [c15]Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan:
A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. ATVA 2008: 222-227 - [c14]Ambar A. Gadkari, Anand Yeolekar, J. Suresh, S. Ramesh, Swarup Mohalik, K. C. Shashidhar:
AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems. CAV 2008: 204-208 - [c13]Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang:
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. DAC 2008: 296-299 - [c12]Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shashidhar:
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. EMSOFT 2008: 89-98 - [c11]Manoranjan Satpathy, Anand Yeolekar, S. Ramesh:
Randomized directed testing (REDIRECT) for Simulink/Stateflow models. EMSOFT 2008: 217-226 - [c10]Deepak D'Souza, Madhu Gopinathan, S. Ramesh, Prahladavaradan Sampath:
Conflict-Tolerant Real-Time Features. QEST 2008: 274-283 - [c9]Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh, K. C. Shashidhar:
Behaviour Directed Testing of Auto-code Generators. SEFM 2008: 191-200 - [c8]Samarjit Chakraborty, S. Ramesh:
Programming and Performance Modelling of Automotive ECU Networks. VLSI Design 2008: 8-9 - 2007
- [c7]Manoranjan Satpathy, S. Ramesh:
Test case generation from formal models through abstraction refinement and model checking. A-MOST 2007: 85-94 - [c6]Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh:
Performance Analysis of FlexRay-based ECU Networks. DAC 2007: 284-289 - [c5]Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh, K. C. Shashidhar:
Testing Model-Processing Tools for Embedded Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2007: 203-214 - [c4]Prahladavaradan Sampath, A. C. Rajeev, K. C. Shashidhar, S. Ramesh:
How to Test Program Generators? A Case Study using flex. SEFM 2007: 80-92 - [c3]S. Ramesh, P. Vignesh V. Ganesan, Gurulingesh Raravi:
A Formal Framework for the Correct-by-construction and Verification of Distributed Time Triggered Systems. SIES 2007: 63-70 - [c2]Manoranjan Satpathy, Michael J. Butler, Michael Leuschel, S. Ramesh:
Automatic Testing from Formal Specifications. TAP 2007: 95-113 - [i1]Ambar A. Gadkari, S. Ramesh:
Automated Synthesis of Assertion Monitors using Visual Specifications. CoRR abs/0710.4698 (2007) - 2005
- [c1]Ambar A. Gadkari, S. Ramesh:
Automated Synthesis of Assertion Monitors using Visual Specifications. DATE 2005: 390-395
Coauthor Index
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last updated on 2024-12-23 19:35 CET by the dblp team
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