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"Fully Row/Column-Parallel In-memory Computing SRAM Macro employing ..."

Jinseok Lee et al. (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492444

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-02

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  dblp key:
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Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma:
Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. VLSI Circuits 2021: 1-2

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