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"An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven ..."

Vivek Garg et al. (2006)

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DOI: 10.1109/VLSID.2006.38

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vlsid/GargCSK06
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design 2006: 507-510

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