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"Area Efficient & High Performance Word Line Segmented Architecture in ..."

Vinay Kumar et al. (2019)

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DOI: 10.1109/VLSID.2019.00093

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja:
Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. VLSID 2019: 437-442

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