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"An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and ..."

Serdar S. Yonar et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830308

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - https://dblp.org/rec/conf/vlsit/YonarFBKMPRACDD22
Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169

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