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"Many-thread aware instruction-level parallelism: architecting shader cores ..."

Ping Xiang et al. (2012)

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DOI: 10.1145/2370816.2370890

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-11

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  dblp key:
  - conf/IEEEpact/XiangYMRZ12
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  persistent URL:
  - https://dblp.org/rec/conf/IEEEpact/XiangYMRZ12
Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou:
Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing. PACT 2012: 449-450

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