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"A Transaction Processing Architecture for Effective Load Balancing ..."

Tetsuro Kakeshita, Susumu Kubo (1996)

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DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2019-08-02

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  dblp key:
  - conf/codas/KakeshitaK96
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  persistent URL:
  - https://dblp.org/rec/conf/codas/KakeshitaK96
Tetsuro Kakeshita, Susumu Kubo:
A Transaction Processing Architecture for Effective Load Balancing Utilizing High Speed Bus. CODAS 1996: 376-379

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