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"Process, Circuit and System Co-optimization of Wafer Level Co-Integrated ..."

Trong Huynh Bao et al. (2019)

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DOI: 10.1145/3316781.3317886

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-08

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  dblp key:
  - conf/dac/BaoVSMRPCYSFKM19
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  persistent URL:
  - https://dblp.org/rec/conf/dac/BaoVSMRPCYSFKM19
Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13

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