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"RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep ..."

Yi-Chen Lu et al. (2021)

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DOI: 10.1109/DAC18074.2021.9586138

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim:
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC 2021: 733-738

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