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"Combining watchdog processor with instruction cache locking for a ..."

Antonio Martí Campoy, Francisco Rodríguez-Ballester (2019)

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DOI: 10.1109/ETFA.2019.8869168

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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Antonio Martí Campoy, Francisco Rodríguez-Ballester:
Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. ETFA 2019: 259-265

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