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"An Optimal Microarchitecture for Stencil Computation with Data Reuse and ..."

Yuze Chi, Peipei Zhou, Jason Cong (2018)

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DOI: 10.1145/3174243.3174964

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-21

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  dblp key:
  - conf/fpga/ChiZC18
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  - https://dblp.org/rec/conf/fpga/ChiZC18
Yuze Chi, Peipei Zhou, Jason Cong:
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). FPGA 2018: 286

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