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"Run-Time Performance Optimization of an FPGA-Based Deduction Engine for ..."
Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam (2001)
- Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam:
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. FPL 2001: 315-325
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