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"Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class ..."

Kazuhiko Terada et al. (2012)

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DOI: 10.1109/FPL.2012.6339229

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano:
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL 2012: 639-642

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