"A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range."

Adnan Gundel, William N. Carr (2007)

Details and statistics

DOI: 10.1109/ISCAS.2007.378067

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.