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"A 5.4 Gb/s clock and data recovery circuit using the seamless loop ..."

Won-Young Lee, Lee-Sup Kim (2011)

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DOI: 10.1109/ISCAS.2011.5937594

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Won-Young Lee, Lee-Sup Kim:
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. ISCAS 2011: 430-433

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