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"Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive ..."

Yang Zhang et al. (2018)

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DOI: 10.1109/BDCLOUD.2018.00059

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  dblp key:
  - conf/ispa/Zhang0TLTW18
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  - https://dblp.org/rec/conf/ispa/Zhang0TLTW18
Yang Zhang, Dan Feng, Zhipeng Tan, Jingning Liu, Wei Tong, Chengning Wang:
Asymmetric-ReRAM: A Low Latency and High Reliability Crossbar Resistive Memory Architecture. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 330-337

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