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"Reconfigurable Low-latency Memory System for Sparse Matricized Tensor ..."

Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna (2021)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2021-09-27

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-2109-08874
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  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-2109-08874
Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna:
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. CoRR abs/2109.08874 (2021)

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