default search action

combined dblp search
author search
venue search
publication search

ask others

"Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time ..."

Chin-Hsin Lin, Marek Syrzycki (2011)

> Home

Details and statistics

DOI: 10.4236/CS.2011.24050

access: open

type: Journal Article

metadata version: 2020-06-08

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/cs/LinS11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cs/LinS11
Chin-Hsin Lin, Marek Syrzycki:
Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution. Circuits Syst. 2(4): 365-371 (2011)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.