default search action

combined dblp search
author search
venue search
publication search

ask others

"Design of Hardware Efficient Reconfigurable Merged Partial Cosine ..."

Hareesh V., T. S. Bindiya (2022)

> Home

Details and statistics

DOI: 10.1007/S00034-021-01877-5

access: closed

type: Journal Article

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cssp/VB22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cssp/VB22
Hareesh V., T. S. Bindiya:
Design of Hardware Efficient Reconfigurable Merged Partial Cosine Modulated Non-uniform Filter Bank Channelizer and its Power Efficient Implementation Using a Novel Approximation Algorithm. Circuits Syst. Signal Process. 41(4): 2118-2135 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.