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<article key="journals/jssc/PayneLBRWPEYGWX05" mdate="2022-03-14">
<author>Robert Payne</author>
<author>Paul E. Landman</author>
<author>Bhavesh Bhakta</author>
<author>Sridhar Ramaswamy</author>
<author>Song Wu</author>
<author>John D. Powers</author>
<author>M. Ulvi Erdogan</author>
<author>Ah-Lyan Yee</author>
<author>Richard Gu</author>
<author>Lin Wu</author>
<author>Yiqun Xie</author>
<author>Bharadwaj Parthasarathy</author>
<author>Keith C. Brouse</author>
<author>Wahed Mohammed</author>
<author>Keerthi Heragu</author>
<author>Vikas Gupta</author>
<author>Lisa Dyson</author>
<author>Wai Lee</author>
<title>A 6.25-Gb/s binary transceiver in 0.13-&#956;m CMOS for serial data transmission across high loss legacy backplane channels.</title>
<pages>2646-2657</pages>
<year>2005</year>
<volume>40</volume>
<journal>IEEE J. Solid State Circuits</journal>
<number>12</number>
<ee>https://doi.org/10.1109/JSSC.2005.856583</ee>
<url>db/journals/jssc/jssc40.html#PayneLBRWPEYGWX05</url>
</article>
</dblp>
