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"veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER ..."

Chandan Kumar Jha et al. (2024)

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DOI: 10.1109/TCSI.2024.3424682

access: closed

type: Journal Article

metadata version: 2024-10-03

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  - https://dblp.org/rec/journals/tcasI/JhaQCSHLMD24
Chandan Kumar Jha, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler:
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024)

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