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"A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling ..."

Zheyi Yuan et al. (2020)

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DOI: 10.1109/TCSII.2020.3001351

access: closed

type: Journal Article

metadata version: 2025-07-04

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Zheyi Yuan, Shiquan Fan, Chenxi Yuan, Li Geng:
A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1664-1668 (2020)

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