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"A bit-level pipelined VLSI architecture for the running order algorithm."

Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao (1997)

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DOI: 10.1109/78.611236

access: closed

type: Journal Article

metadata version: 2020-03-10

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  - https://dblp.org/rec/journals/tsp/ChenCH97
Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao:
A bit-level pipelined VLSI architecture for the running order algorithm. IEEE Trans. Signal Process. 45(8): 2140-2144 (1997)

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