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"A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration ..."

Fujun Bai et al. (2023)

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DOI: 10.1109/TVLSI.2022.3219437

access: closed

type: Journal Article

metadata version: 2023-07-30

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  - https://dblp.org/rec/journals/tvlsi/BaiWJGYWLRS23
Fujun Bai, Song Wang, Xuerong Jia, Yixin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun:
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 128-141 (2023)

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