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Publication search results
found 173 matches
- 1998
- Thorsten Adler, Juergen Schaeuble:
An Interactive Router for Analog IC Design. DATE 1998: 414-420 - Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto:
A Model for System-Level Timed Analysis and Profiling. DATE 1998: 204-210 - Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths. DATE 1998: 266-272 - Bogdan G. Arsintescu, Ralph H. J. M. Otten:
Constraints Space Management for the Layout of Analog IC's. DATE 1998: 971-972 - Anupam Basu, Rainer Leupers, Peter Marwedel:
Register-Constrained Address Computation in DSP Programs. DATE 1998: 929-930 - Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano:
Address Bus Encoding Techniques for System-Level Power Optimization. DATE 1998: 861-866 - Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis:
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. DATE 1998: 729-735 - Alessandro Bogliolo, Luca Benini, Giovanni De Micheli:
Characterization-Free Behavioral Power Modeling. DATE 1998: 767-773 - T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian:
Built-In Self-Test with an Alternating Output. DATE 1998: 180-184 - Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Fault Analysis in Networks with Concurrent Error Detection Properties. DATE 1998: 957-958 - Jörg Böttger, Karlheinz Agsteiner, Dieter Monjau, Sören Schulze:
An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse. DATE 1998: 303-310 - Oliver Bringmann, Wolfgang Rosenstiel:
Cross-Level Hierarchical High-Level Synthesis. DATE 1998: 451-456 - Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier:
A Programmable Multi-Language Generator for CoDesign. DATE 1998: 927-928 - Francky Catthoor:
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions. DATE 1998: 709-714 - V. Chandramouli, Jesse Whittemore, Karem A. Sakallah:
AFTA: A Formal Delay Model for Functional Timing Analysis. DATE 1998: 350-355 - Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee:
Functional Scan Chain Testing. DATE 1998: 278-283 - Alexander Chatzigeorgiou, Spiridon Nikolaidis:
Collapsing the Transistor Chain to an Effective Single Equivalent Transistor. DATE 1998: 2-6 - David Ihsin Cheng:
On Removing Multiple Redundancies in Combinational Circuits. DATE 1998: 738-742 - Chris C. N. Chu, D. F. Wong:
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485 - Jason Coppens, Dhamin Al-Khalili, Côme Rozon:
VHDL Modelling and Analysis of Fault Secure Systems. DATE 1998: 148-152 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-677 - João Paulo Costa, Mike Chou, L. Miguel Silveira:
Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's. DATE 1998: 892-898 - Olivier Coudert:
A New Paradigm for Dichotomy-based Constrained Encoding. DATE 1998: 830-834 - Jean Michel Daga, E. Ottaviano, Daniel Auvergne:
Temperature Effect on Delay for Low Voltage Applications. DATE 1998: 680-685 - Bharat P. Dave, Niraj K. Jha:
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. DATE 1998: 118-124 - Juan Carlos Diaz, Pierre Plaza, Jesus Crespo:
ATM Traffic Shaper: ATS. DATE 1998: 96-101 - Guido Dröge, Manfred Thole, Ernst-Helmut Horneber:
EASY - a System for Computer-Aided Examination of Analog Circuits. DATE 1998: 644-648 - Josef Eckmüller, Martin Groepl, Helmut E. Graeb:
Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE 1998: 636-643 - George Economakos, George K. Papakonstantinou, Panayotis Tsanakas:
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. DATE 1998: 933-934 - C. A. J. van Eijk:
Sequential Equivalence Checking without State Space Traversal. DATE 1998: 618-623
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retrieved on 2024-12-29 05:56 CET from data curated by the dblp team
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