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29th DAC 1992: Anaheim, California, USA
- Daniel G. Schweikert:
Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992. IEEE Computer Society Press 1992, ISBN 0-8186-2822-7
Electrical Analysis
- Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits. 2-7 - Yun-Cheng Ju, Resve A. Saleh:
Incremental Circuit Simulation Using Waveform Relaxation. 8-11 - T. A. Johnson, Albert E. Ruehli:
Parallel Waveform Relaxation of Circuits with Global Feedback Loops. 12-15
Test Generation
- Kwang-Ting Cheng, Hi-Keung Tony Ma:
On the Over-Specification Problem in Sequential ATPG Algorithms. 16-21 - Miron Abramovici, Krishna B. Rajan, David T. Miller:
Freeze!: A New Approach for Testing Sequential Circuits. 22-25 - Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. 26-29
Two Level Logic Synthesis
- Andisheh Sarabi, Marek A. Perkowski:
Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks. 30-35 - Olivier Coudert, Jean Christophe Madre:
Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions. 36-39 - Bill Lin, Olivier Coudert, Jean Christophe Madre:
Symbolic Prime Generation for Multiple-Valued Functions. 40-44
Tutorial
- Dwight D. Hill, Ewald Detjens:
FPGA Design Principles (A Tutorial). 45-46
Partitioning and Floorplanning
- Jason Cong, Lars W. Hagen, Andrew B. Kahng:
Net Partitions Yield Better Module Partitions. 47-52 - Minshine Shih, Ernest S. Kuh, Ren-Song Tsay:
Performance-Driven System Partitioning on Multi-Chip Modules. 53-56 - Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. 57-61 - Ting-Chi Wang, D. F. Wong
:
A Graph Theoretic Technique to Speed up Floorplan Area Optimization. 62-68 - Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. 69-74
Interconnect Simulation
- Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson:
Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time. 75-80 - Shen Lin, Ernest S. Kuh:
Transient Simulation of Lossy Interconnect. 81-86 - Vivek Raghavan, J. Eric Bracken, Ronald A. Rohrer:
AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems. 87-92 - David D. Ling, S. Kim, J. White:
A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect. 93-98
Scheduling and Allocation
- Mehrdad Nourani, Christos A. Papachristou:
Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. 99-105 - Minjoong Rim, Rajiv Jain:
Representing Conditional Branches for High-Level Synthesis Applications. 106-111 - Kazutoshi Wakabayashi, Hirohito Tanaka:
Global Scheduling Independent of Control Dependencies Based on Condition Vectors. 112-115 - Catherine H. Gebotys:
Optimal Scheduling and Allocation of Embedded VLSI Chips. 116-119 - Minjoong Rim, Rajiv Jain, Renato De Leone:
Optimal Allocation and Binding in High-Level Synthesis. 120-123 - Werner Geurts, Francky Catthoor, Hugo De Man:
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. 124-127
Panel
- Peter Hillen:
Is Technology-Independent Design Really Practical? (Panel Abstract). 128
Concurrent Engineering
- David Becker, Raj K. Singh, Stephen G. Tell:
An Engineering Environment for Hardware/Software Co-Simulation. 129-134 - Ing-Jer Huang, Alvin M. Despain:
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. 135-140
New Approaches to Placement
- Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel:
APT: An Area-Performance-Testability Driven Placement Algorithm. 141-146 - Tong Gao, Pravin M. Vaidya, C. L. Liu:
A Performance Driven Macro-Cell Placement Algorithm. 147-152 - Rung-Bin Lin, Eugene Shragowitz:
Fuzzy Logic Approach to Placement Problem. 153-158
Deley-Fault Testing
- Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal:
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. 159-164 - Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. 165-172 - Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. 173-176 - Irith Pomeranz, Sudhakar M. Reddy:
At-Speed Delay Testing of Synchronous Sequential Circuits. 177-181
Synthesis Systems and Representations
- Wayne H. Wolf, Andrés Takach, Chun-Yao Huang, Richard Manno, Ephrem Wu:
The Princeton University Behavioral Synthesis System. 182-187 - A. Stoll, Peter Duzy:
High-Level Synthesis from VHDL with Exact Timing Constraints. 188-193 - Andrew Seawright, Forrest Brewer
Synthesis from Production-Based Specifications. 194-199
Panel
- Ronald Collet:
Which ASIC Technology Will Dominate the 1990's (Panel Abstract). 200
Asymptotic Waveform Evaluation
- Eli Chiprout, Michel S. Nakhla:
Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks. 201-206 - Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage:
On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. 207-212 - John Y. Lee, Ronald A. Rohrer:
AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform Evaluation. 213-218
System-Level Synthesis
- Frank Vahid, Daniel Gajski:
Specification Partitioning for System Design. 219-224 - Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. 225-230 - Yung-Hua Hung, Alice C. Parker:
High-Level Synthesis with Pin Constraints for Multiple-Chip Designs. 231-234 - D. Sreenivasa Rao, Fadi J. Kurdahi:
Partitioning by Regularity Extraction. 235-238
Performance Issues in Logic Synthesis
- Meng-Lin Yu, P. A. Subrahmanyam:
A Path-Oriented Approach for Reducing Hazards in Asynchronous Designs. 239-244 - Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. 245-248 - Hsi-Chuan Chen, David Hung-Chang Du, Siu-Wing Cheng:
Circuit Enhancement by Eliminating Long False Paths. 249-252 - Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob K. White:
Estimation of Average Switching Activity in Combinational and Sequential Circuits. 253-259
Panel
- William Lattin:
Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract). 260
High-Level Test Generation
- Jaushin Lee, Janak H. Patel:
Hierarchical Test Generation under Intensive Global Functional Constraints. 261-266 - Jean François Santucci, Gérard Dray, Norbert Giambiasi, Marc Boumédine:
A Methodology to Reduce the Computational Cost of Behavioral Test Pattern Generation. 267-272 - Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir:
Automatic Test Knowledge Extraction from VHDL (ATKET). 273-278
Allocation and Binding
- Ganesh Krishnamoorthy, John A. Nestor:
Data Path Allocation using an Extended Binding Model. 279-284 - Brent Gregory, Don MacMillen, Dennis Fogg:
ISIS: A System for Performance Driven Resource Sharing. 285-290 - Elke A. Rundensteiner, Daniel Gajski:
Functional Synthesis Using Area and Delay Optimization. 291-296
Panel
- Rick Potter:
Why it doesn't work for CAD (Panel Abstract). 297
Tutorial
- Gerry Langeler:
Directions to Watch in Design Technology (Tutorial Abstract). 298
Design Verification and Compaction
- Pradeep Batra, David Cooke:
Hcompare: A Hierarchical Netlist Comparison Program. 299-304 - Georg Peltz:
An Interpreter for General Netlist Design Rule Checking. 305-310 - Cyrus Bamji, Ravi Varadarajan:
Hierarchical Pitchmatching Compaction Using Minimum Design. 311-317 - David G. Boyer:
Process Independent Constraint Graph Compaction. 318-322 - Wonjong Kim, Joohack Lee, Hyunchul Shin:
A New Hierarchical Layout Compactor Using Simplified Graph Models. 323-326
Fault Simulation and Fault Diagnosis
- Dong-Ho Lee, Sudhakar M. Reddy:
On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. 327-331 - Soumitra Bose, Prathima Agrawal:
Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. 332-335 - Hyung Ki Lee, Dong Sam Ha:
HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits. 336-340 - Amitava Majumdar, Sarma Sastry:
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. 341-346 - Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh:
Exact Evaluation of Diagnostic Test Resolution. 347-352 - Sreejit Chakravarty, Minsheng Liu:
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. 353-356 - Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A Novel Approach to Delay-Fault Diagnosis. 357-360
FPGA Synthesis
- Kevin Chung, Jonathan Rose:
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. 361-367 - Prashant Sawkar, Donald E. Thomas:
Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. 368-373 - Ulf Schlichtmann, Franc Brglez, Michael Hermann:
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. 374-379 - Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
An Improved Synthesis Algorithm for Multiplexor-Based PGA's. 380-386
Tutorial
- Patrick M. Hefferan, Steve Sapiro:
Acquiring and Maintaining State-of-the-Art DA Systems. 387-392
Timing Optimization and Verification
- Ichiang Lin, John A. Ludwig, Kwok Eng:
Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches. 393-398 - Thomas G. Szymanski:
Computing Optimal Clock Schedules. 399-404 - Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
On the Temporal Equivalence of Sequential Circuits. 405-409 - Tod Amon, Gaetano Borriello:
An Approach to Symbolic Timing Verification. 410-413
Discrete Simulation
- Benoit A. Gennart, David C. Luckham:
Validating Discrete Event Simulations Using Event Pattern Mappings. 414-419 - Yun Sik Lee, Peter M. Maurer:
Two New Techniques for Compiled Multi-Delay Logic Simulation. 420-423 - Larry G. Jones:
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator. 424-427 - Fumiyasu Hirose:
Performance Evaluation of an Event-Driven Logic Simulation Machine. 428-431 - David A. Zein, Oliver P. Engel, Gary S. Ditlow:
HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. 432-437
Multi-Level Logic Synthesis
- Wen-Jun Hsu, Wen-Zen Shen:
Coalgebraic Division for Multilevel Logic Synthesis. 438-442 - Kuang-Chien Chen, Masahiro Fujita:
Efficient Sum-to-One Subsets Algorithm for Logic Optimization. 443-448 - Abdul A. Malik:
Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization. 449-453 - Michael J. Batek, John P. Hayes:
Test-Set Preserving Logic Transformations. 454-458
Panel
- Ronald Collet:
Design and Integration Services (Panel Abstract). 459
DA for High-Speed Packaging
- Albert E. Ruehli, Hansruedi Heeb:
Challenges and Advances in Electrical Interconnect Analysis. 460-465 - Paul D. Franzon, Slobodan Simovich, Michael B. Steer, Mark Basel, Sharad Mehrotra, Tom Mills:
Tools to Aid in Wiring Rule Generation for High Speed Interconnects. 466-471 - Norman H. Chang, Keh-Jeng Chang, John Leo, Ken Lee, Soo-Young Oh:
IPDA: Interconnect Performance Design Assistant. 472-477
Technology Mapping in Logic Synthesis
- Wing Ning Li, Andrew Lim, Prathima Agrawal, Sartaj Sahni:
On the Circuit Implementation Problem. 478-483 - David S. Kung, Robert F. Damiano, Theresa A. Nix, David J. Geiger:
BDDMAP: A Technology Mapper Based on a New Covering Algorithm. 484-487 - John P. Fishburn:
LATTIS: An Iterative Speedup Heuristic for Mapped Logic. 488-491 - Kamal Chaudhary, Massoud Pedram:
A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints. 492-498
Panel
- Arny Goldfein:
Why is Today's CAD Inadequate for Designing Tomorrow's Computers (Panel Abstract). 499
Frameworks
- Margarida F. Jacome, Stephen W. Director:
Design Process Management for CAD Frameworks. 500-505 - Robert Beggs, John Sawaya, Catharine Ciric, Julius Etzl:
Automated Design Decision Support System. 506-511 - Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design. 512-517
Global Issues in Routing
- Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho:
Zero Skew Clock Net Routing. 518-523 - Takashi Mitsuhashi, Ernest S. Kuh:
Power and Ground Network Topology Optimization for Cell Based VLSIs. 524-529 - Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
FARM: An Efficient Feed-Through Pin Assignment Algorithm. 530-535
Path Delay Analysis
- Jon Frankle:
Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing. 536-542 - Siu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang Du, Andrew Lim:
The Role of Long and Short Paths in Circuit Performance Optimization. 543-548 - Srinivas Devadas, Kurt Keutzer, Sharad Malik
Certified Timing Verification and the Transition Delay of a Logic Circuit. 549-555
Sequential Logic Synthesis
- Maurizio Damiani, Giovanni De Micheli:
Recurrence Equations and the Optimization of Synchronous Logic Circuits. 556-561 - Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal:
Finite State Machine Synthesis with Fault Tolerant Test Function. 562-567 - Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Solving the State Assignment Problem for Signal Transition Graphs. 568-572 - Irith Pomeranz, Kwang-Ting Cheng:
State Assignment Using Input/Output Functions. 573-577
Panel
- L. Lanzo:
Frameworks - User's Perspective (Panel Abstract). 578
Multi-Layer Channel and Over-the-Cell Routing
- Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee:
A New Efficient Approach to Multilayer Channel Routing Problem. 579-584 - Takashi Fujii, Yoko Mima, Tsuneo Matsuda, Takeshi Yoshimura:
A Multi-Layer Channel Router with New Style of Over-the-Cell Routing. 585-588 - Tai-Tsung Ho:
New Models for Four- and Five-Layer Channel Routing. 589-593 - Cliff Yungchin Hou, C. Y. Roger Chen:
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing. 594-599 - Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh:
Over-the-Cell Channel Routing for High Performance Circuits. 600-603 - Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh:
Over-the-Cell Routers for New Cell Model. 604-607
Automated Approaches to Formal Verification of Hardware
- Yung-Te Lai, Sarma Sastry:
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. 608-613 - Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal. 614-619 - Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. 620-623 - M. Ray Mercer, Rohit Kapur, Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations. 624-627 - June-Kyung Rho, Fabio Somenzi:
Inductive Verification of Iterative Systems. 628-633 - Yew-Hong Leong, William P. Birmingham:
The Automatic Generation of Bus-Interface Models. 634-637
Advances in High-Level Synthesis
- Usha Prabhu, Barry M. Pangrle:
Superpipelined Control and Data Path Synthesis. 638-643 - Rajiv Dutta, Jayanta Roy, Ranga Vemuri:
Distributed Design-Space Exploration for High-Level Synthesis Systems. 644-650 - Ruchir Puri, Jun Gu:
An Efficient algorithm for Microword Length Minimization. 651-656 - Reinaldo A. Bergamaschi, Donald A. Lobo, Andreas Kuehlmann:
Control Optimization in High-Level Synthesis Using Behavioral Don't Cares. 657-661 - Ramesh Karri
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. 662-665
Tutorial - EDIF/CFI - A User's Perspective
- Hilary J. Kahn, Richard Goldman:
The Electronic Design Interchange Format EDIF: Present and Future. 666-671 - Todd J. Scallan:
CAD Framework Initiative - A User Perspective. 672-675
Routing for Special Applications
- Ryosuke Okuda, Sumio Oguri:
An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style. 676-681 - Youlin Liao, Stan Chow:
Routing Considerations in Symbolic Layout Synthesis. 682-686 - Soohong Kim, Robert Michael Owens, Mary Jane Irwin:
Experiments with a Performance Driven Module Generator. 687-690 - Mikael Palczewski:
Plane Parallel a Maze Router and Its Application to FPGAs. 691-697
Issues in Analog CAD
- Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar:
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. 698-703 - Abhijit Dharchoudhury, Sung-Mo Kang:
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. 704-709 - Keith Nabors, Jacob K. White:
Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics. 710-715
Panels
- John P. Eurich:
The State of EDA Standards (Panel Abstract). 716 - Charles A. Shaw:
Manufacturing Interface (Panel Abstract). 717
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