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22nd IOLTS 2016: Sant Feliu de Guixols, Spain
- 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Spain, July 4-6, 2016. IEEE 2016, ISBN 978-1-5090-1507-8
- Serhiy Avramenko, Matteo Sonza Reorda
, Massimo Violante, Görschwin Fey
On the robustness of DCT-based compression algorithms for space applications. 1-2 - Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Jimson Mathew, Abusaleh M. Jabir:
Analytic models for crossbar read operation. 3-4 - Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva:
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. 5-6 - Zeinab Mahdavi, Zahra Shirmohammadi
ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips. 7-8 - Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas:
An on-line test solution for addressing interconnect shorts in on-chip networks. 9-12 - Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi
An soft error propagation analysis considering logical masking effect on re-convergent path. 13-16 - Jiajing Cai, Basel Halak
Analysis of BTI aging of level shifters. 17-18 - Maha Kooli, Giorgio Di Natale, Alberto Bosio:
Cache-aware reliability evaluation through LLVM-based analysis and fault injection. 19-22 - Romain Champon, Vincent Beroulle, Athanasios Papadimitriou
Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices. 23-24 - Zhen Gao, Pedro Reviriego, Juan Antonio Maestro
Efficient fault tolerant parallel matrix-vector multiplications. 25-26 - David Trilla
Resilient random modulo cache memories for probabilistically-analyzable real-time systems. 27-32 - Manish Rana, Ramon Canal
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation. 33-38 - Hailong Jiao, Yongmin Qiu, Volkan Kursun
Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. 39-42 - Alain Bravaix
Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodes. 43-46 - Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel:
Activity profiling: Review of different solutions to develop reliable and performant design. 47-50 - Boukary Ouattara, Olivier Héron, Chiara Sandionigi:
Fine-grain analysis of the parameters involved in aging of digital circuits. 51-53 - K. Chibani, Michele Portolan
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. 54-59 - Jaime Espinosa
Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection. 60-65 - Mojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi Baradaran Tahoori, Giorgio Di Natale:
Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models. 66-71 - George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Ronny Morad:
ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors. 72-77 - Yumin Zhou, Oliver Bringmann, Wolfgang Rosenstiel:
Flexible in-silicon checking of run-time programmable assertions. 78-83 - Yutaka Masuda, Masanori Hashimoto
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. 84-89 - Bartomeu Alorda
On-line write margin estimator to monitor performance degradation in SRAM cores. 90-95 - Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos:
Recovery of performance degradation in defective branch target buffers. 96-102 - Mohd Syafiq Mispan
NBTI aging evaluation of PUF-based differential architectures. 103-108 - Shoba Gopalakrishnan, Virendra Singh:
REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. 109-114 - Mauricio D. Gutierrez, Vasileios Tenentes
Susceptible workload driven selective fault tolerance using a probabilistic fault model. 115-120 - Konstantin Tscherkaschin, Theodor Hillebrand, Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen:
Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS process. 121-125 - Ajay Kapoor, Nur Engin, Johan Verdaasdonk:
Leakage mitigation for low power microcontroller design in 40nm for Internet-of-Things (IoT). 126-129 - Michael Nicolaidis, Michael G. Dimopoulos:
Advanced double-sampling architectures. 130-132 - Hans-Joachim Wunderlich, Claus Braun, Alexander Schöll:
Pushing the limits: How fault tolerance extends the scope of approximate computing. 133-136 - Erol Koser, Walter Stechele:
Tackling long duration transients in sequential logic. 137-142 - Xiang Chen, Wenhui Yang, Ming Zhao, Jing Wang:
HLS-based sensitivity-inductive soft error mitigation for satellite communication systems. 143-148 - Dimitris Theodoropoulos, Nektarios Kranitis
An efficient LDPC encoder architecture for space applications. 149-154 - Luca Sterpone
Scalable FPGA graph model to detect routing faults. 155-160 - Sujay Pandey, Suvadeep Banerjee
Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks. 161-166 - Riccardo Cantoro
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks. 167-172 - Alessandro Savino, Stefano Di Carlo, Alessandro Vallero, Gianfranco Politano, Dimitris Gizopoulos, Adrian Evans:
RIIF-2: Toward the next generation reliability information interchange format. 173-178 - Elena Ioana Vatajelu
STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation. 179-184 - Marko S. Andjelkovic
SET response of a SEL protection switch for 130 and 250 nm CMOS technologies. 185-190 - Arash Nejat, David Hély
Reusing logic masking to facilitate path-delay-based hardware Trojan detection. 191-192 - Ghislain Takam Tchendjou, Rshdee Alhakim, Emmanuel Simeu, Fritz Lebowsky:
Evaluation of machine learning algorithms for image quality assessment. 193-194 - Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka:
An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs. 195-198 - Patryk Skoncej, Felix Mühlbauer
Feasibility of software-based repair for program memories. 199-202 - Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Hardware Trojans classification for gate-level netlists based on machine learning. 203-206 - Alejandro Serrano-Cases
On the influence of compiler optimizations in the fault tolerance of embedded systems. 207-208 - Theodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, Steffen Paul, Dagmar Peters-Drolshagen:
Online monitoring of NBTI and HCD in beta-multiplier circuits. 209-210 - Andreina Zambrano, Hans G. Kerkhoff:
Online monitoring of the maximum angle error in AMR sensors. 211-212 - Stefano Esposito
Online time interference detection in mixed-criticality applications on multicore architectures using performance counters. 213-214 - Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali
Power-side-channel analysis of carbon nanotube FET based design. 215-218 - Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Redesign for untrusted gate-level netlists. 219-220 - Rongmei Chen, Enxia Zhang
Single-event performance of differential flip-flop designs and hardening implication. 221-226 - Panagiotis Sismanoglou, Dimitris Nikolos:
Conditional soft-edge flip-flop for SET mitigation. 227-232 - Satyadev Ahlawat
A high performance scan flip-flop design for serial and mixed mode scan test. 233-238 - Hyunmin Kim, Seokhie Hong, Bart Preneel
Binary decision diagram to design balanced secure logic styles. 239-244 - Lake Bu, Mark G. Karpovsky:
A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems. 245-250 - Mohammad Saleh Samimi, Ehsan Aerabi, Zahra Kazemi
Hardware enlightening: No where to hide your Hardware Trojans! 251-256
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