default search action
13th ICECS 2006: Nice, France
- 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. IEEE 2006, ISBN 1-4244-0395-2
- H. J. Kadim, Lacina M. Coulibaly:
Distributed RLC Interconnect: Analytical Modelling Expressions for Crosstalk Noise Estimation. 1-4 - Ali Abuelmaatti, Iain Thayne:
A New RF SiCMOS SDD Model for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear Parameters. 5-8 - Patrick Pittet
, Guo-Neng Lu, Laurent Quiquerez:
Noise Modeling For Charge Amplification and Sampling. 9-12 - Luís Nero Alves
General Model for the Deployment of Time-Delay Elements in Transistorized Electronic Circuits. 13-16 - Lubomír Brancík
Multiconductor Transmission Lines Sensitivity via Two-Dimensional Laplace Transform. 17-20 - Ahmad Mizannojehdehi, Maitham Shams, Tofy Mussivand:
Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System. 21-24 - Guillaume Lesbros, Mohamad Sawan:
Multiparameters monitoring for long term in-vivo characterization of electrode-tissues contacts. 25-28 - Cihun-Siyong Alex Gong, Muh-Tian Shiue, Chun-Hsien Su, Yin Chang:
An Efficient Micro-Stimulator Array Using Unitary-Size DAC With Adiabatic Baseband Scheme. 29-32 - Cihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-Lung Lo, Muh-Tian Shiue:
Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. 33-36 - Ioannis Pachnis, Andreas Demosthenous, Nick Donaldson
Comparison of Transconductance Reduction Techniques for the Design of a Very Large Time-Constant CMOS Integrator. 37-40 - Lucien J. Breems, Robert H. M. van Veldhoven, Kathleen Philips, Robert Rutten, Gunnar Wetzker:
Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers. 41-45 - Stijn Reekmans, Benoit Catteau, Pieter Rombouts, Ludo Weyten:
Quadrature Mismatch Shaping with a Complex, Data Directed Swapper. 46-49 - Susana Patón
Design of Cascaded Continuous-Time Sigma-Delta Modulators. 50-53 - Niall Duncan, Anthony Dunne, Michael Peter Kennedy
Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC. 54-57 - Ana Rusu
Sigma-Delta Solutions for Future Wireless Handields. 58-61 - Saul Rodriguez
Analysis of Wideband CMOS Low Noise Amplifiers using current-reuse configuration. 62-65 - Ouail El-Gharniti, Eric Kerherve
Concurrent Dual-Band Low Noise Amplifier for 802.11a/g WLAN applications. 66-69 - Cristian Pavão Moreira, Eric Kerhervé
Design and Implementation of BiFET LNAs for W-CDMA / IEEE 802.11a Applications. 70-73 - Nikolaos Mavredakis, Matthias Bucher
Inversion-Coefficient Based Design of RF CMOS Low-Noise Amplifiers. 74-77 - Chung-Yu Wu, Fadi Riad Shahroury
A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network. 78-81 - Phanumas Khumsat, Apisak Worapishet, Klanarong Noulkaew, Theerachet Soorapanth:
Differential-Mode/Common-Mode Feedforward Transconductor for Low-Voltage Gm-C filters. 82-85 - Belén Calvo, Santiago Celma, Maria Teresa Sanz
A High-Linear Low-voltage CMOS Tunable Transconductor for VHF Filtering. 86-89 - Andrea Maniero, Andrea Bevilacqua
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency. 90-93 - Saleh R. Al-Araji, Kahtan A. Mezher
Automatic Tuning of Continuous Time Adaptive Bandpass Filter. 94-97 - Masood ul-Hasan, Yichuang Sun:
Oscillation-Based Test Structure and Method for OTA-C Filters. 98-101 - Ainhoa Cortés
An FFT Core for DVB-T/DVB-H Receivers. 102-105 - Muhammad E. S. Elrabaa:
An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications. 106-109 - George Economakos, Kostas Anagnostopoulos, Isidoros Sideris:
A Methodology for Design Space Exploration in Embedded DSP Applications. 110-113 - Houssem Hajji, Adel Ghazel:
Design and Implementation of a Correlation-based DSP Software for Narrowband Power Line Communication Receiver. 114-118 - Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari
A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor. 119-122 - Anas A. Hamoui, Franco Maloberti:
Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications. 123-127 - Olujide A. Adeniran, Andreas Demosthenous:
A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs. 128-131 - Athon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund:
Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers. 132-135 - Alan Bannon, Anthony Dunne, Daniel O'Hare
A 2nd Order 1-bit Complex Switched Capacitor Sigma-Delta ADC with 90dB SNDR in a 180kHz Bandwidth. 136-139 - Junho Moon, Seunghwi Jung, Sanghoon Hwang, Minkyu Song:
A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction Technique. 140-143 - Anthony Kolar, Tarik Graba, Andréa Pinna, Olivier Romain
An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor. 144-147 - Mazen Youssef, Camille Diou
CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver. 148-151 - Luca Sterpone
An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture. 152-155 - Nana B. Sam, Sally A. McKee, Prabhakar Kudva:
Rethinking Processor Design: Parameter Correlations. 156-159 - Koji Inoue:
Supporting A Dynamic Program Signature: An Intrusion Detection Framework for Microprocessors. 160-163 - Faycal Bensaali
Power Modeling and Efficient FPGA Implementation of Color Space Conversion. 164-167 - Paolo Zicari, Pasquale Corsonello
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. 168-171 - William N. Chelton, Mohammed Benaissa:
Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach. 172-175 - Tommaso Balercia, Andrea Zitti, Henry Francesconi, Simone Orcioni
FPGA Implementations of a Simplified Retinex Image Processing Algorithm. 176-179 - Luciano Volcan Agostini
High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs. 180-183 - Ulrich L. Rohde, Ajay K. Poddar:
Multi-Mode Wideband Voltage Controlled Oscillators. 184-187 - Domenico Zito, Domenico Pepe
High-Performance VCO for 5-GHz WLANs in 0.35 μm CMOS Standard Technology. 188-191 - Owen Casha
Design of a 1.2 V Low Phase Noise 1.6 GHz CMOS Buffered Quadrature Output VCO with Automatic Amplitude Control. 192-195 - Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi
Analysis of Harmonic Distortion in the Colpitts Oscillator. 196-199 - Yukio Hattori, Hiroki Sato, Akira Hyogo, Keitaro Sekine:
A Design Approach for Low Phase Noise 5GHz Complementary Quadrature Oscillator. 200-203 - Gianluca Giustolisi, Gaetano Palumbo, Christian Falconi
NMOS Low Drop-Out Regulator with Dynamic Biasing. 204-207 - Christian Jesús B. Fayomi, Stephen J. Stratz:
Novel Approach to Low-Voltage Low-Power Bandgap Reference Voltage in Standard CMOS Process. 208-211 - Andrea Boni, Alessandro Carboni, Alessio Facen:
Design of fuel-cell powered DC-DC converter for portable applications in digital CMOS technology. 212-215 - Joseph T.-s. Tsai, Herming Chiueh:
High Linear Voltage References for on-chip CMOS Temperature Sensor. 216-219 - Tzu-Ming Wang, Ming-Dou Ker, Steve Yeh, Ya-Chun Chang:
Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory. 220-223 - Jesse P. Somann, Yong C. Kim:
Characterization of In-Phase/Quad-Phase Digital Downconversion Via Special Sampling Scheme. 224-227 - Michael Hofstätter, Ahmed Nabil Belbachir, Ernst Bodenstorfer
Multiple Input Digital Arbiter with Timestamp Assignment for Asynchronous Sensor Arrays. 228-231 - Kimmo Järvinen, Juha Forsten, Jorma Skyttä:
Efficient Circuitry for Computing τ-adic Non-Adjacent Form. 232-235 - Mladen Vucic, Goran Molnar:
Time-Domain Synthesis of IIR Phase Equalizers. 236-239 - Akihiko Yoneya:
Spread Spectrum PWM Signal Generator for Fully Digital Audio Amplifier. 240-243 - Ahmed S. Elwakil
Explaining Hysteresis in Electronic Circuits: Robust Simulation and Design Examples. 244-247 - Mohsen Moezzi
A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. 248-251 - Lei Zhang, Zhiping Yu, Xiangqing He:
Hazard Free Sawtooth Oscillator and Its Application in Ultra Low Current Monitoring. 252-255 - Nikolaos Charalampidis, Khaled Hayatleh, Bryan L. Hart, F. John Lidgey:
A wide bandwidth voltage-follower with low distortion and high slew rate. 256-259 - Chung-Yuan Chen, Tai-Ping Sun:
A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application. 260-263 - Hamed Aminzadeh, Reza Lotfi, Somayyeh Rahimian:
Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers. 264-267 - Cong-Kha Pham
Simple Logic Threshold Conversion Circuits. 268-271 - Sarang Kazeminia
High Speed High Precision Voltage-Mode MAX and MIN Circuits. 272-275 - Fabrice Gayral, Elisabeth Delevoye
A Sigma-Delta closed-loop digital microfluxgate magnetometer. 276-279 - David Guilherme, Nuno V. Caldeira, João Risques:
Fully Integrated Headphone Detector. 280-283 - Radoslaw Klosinski:
Periodically time-varying two-terminals at a steady state, description and identification. 284-287 - Fabrice Guigues, Edith Kussener, Alexandre Malherbe, Benjamin Duval:
Sub-1V Oguey's Current Reference Without Resistance. 288-291 - Merih Yildiz
CMOS Realization of a Quantized-Output Classifier Circuit. 292-295 - Maria José Pereira Dantas
Biobjective Hybrid Evolutionary Algorithm Applied to Resonator Filters of Arbitrary Topology. 296-299 - Igor M. Filanovsky, Chris J. M. Verhoeven:
Transition from Sinusoidal to Relaxation Oscillations in Emitter-Coupled Multivibrators. 300-303 - Paul Bustamante, Mikel Osinalde, Jon del Portillo, Gonzalo Solas:
Wireless System for Temperature Measurement in Wheels, based on the ISM Band. 304-309 - Vincent Frick, Joris Pascal, Luc Hébrard, Jean-Philippe Blonde:
Integrated instrumental chain for magnetic pulse measurement in strong static field environment. 310-313 - Alexander Belenky, Alexander Fish
Global Shutter CMOS Image Sensor With Wide Dynamic Range. 314-317 - Shahram Mohammad Nejad, Maryam Pourmahyabadi:
The Performance Modeling of Ring Laser Gyro In Inertial Navigation. 318-321 - Cyril Joubert, Jean-François Bercher
Contributions to the analysis and design of an ADPLL. 322-325 - Mohsen Choubani, Fethi Choubani, Ali Gharsallah, Jacques David, Nikos E. Mastorakis:
Analysis and Design of Antireflection and Frequency Selective Surfaces with Stratified and inhomogeneous media. 326-330 - Nathalie Deltimple, Eric Kerherve
Design of a SiGe Reconfigurable Power Amplifier for RF Applications: Device and Multi-standard Considerations. 331-334 - Sergio Gagliolo, Giacomo Pruzzo
Differential Cross-Coupled CMOS VCOs with Resistive and Inductive Tail Biasing. 335-338 - Thierry Dupire, Louis-François Tanguay, Mohamad Sawan:
Low power CMOS transmitter for biomedical sensing devices. 339-342 - Elias Hanna, Pierre Jarry, Eric Kerherve
A novel compact dual-mode bandpass filter using fractal shaped resonators. 343-346 - Ali Messaoud, Mohamed Ben Messaoud, Abdennaceur Kachouri, Faiçal Sellami:
Fuzzy logic based system for classification of atrial fibrillation cardiac arrhythmias. 347-350 - Cihun-Siyong Alex Gong, Muh-Tian Shiue, Yin Chang:
Design And Implementation Of A Monolithic Programme-Controlled System For Retinal Prosthesis. 351-354 - H. Ben M'Hadheb, Ali Douik
Reduction of color variability in color image segmentation. 355-358 - Nicoleta Baxan
High-Resolution 1H NMR Micro spectroscopy using an Implantable Micro-coil. 359-362 - Pedro Gómez
An FPGA-based genetic microarray processing device. 363-366 - Genaro Carrillo, Guo-Neng Lu, Patrick Pittet
CMOS BDJ detector array with charge preamplifiers for sensitive biochemical analysis. 367-370 - Chin-Long Wey, Chi-Shu Huang, Shaolei Quan:
Design of Reliable CMOS Phase-Locked Loops. 371-374 - Jeong Beom Kim:
Novel Current Sensing Circuit for IDDQ Testing. 375-378 - Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Algorithms for Compositions of Arithmetic Transforms and Their Extensions. 379-382 - Mikaël Cimino, Magali De Matos, Hervé Lapuyade, Thierry Taris, Yann Deval
A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network Applications. 383-386 - Makoto Ikeda, Hiroshi Yamauchi, Kunihiro Asada:
Tamper Resistivity Analysis for Nano-meter LSI with Process Variations. 387-390 - Ji Fan, Matthieu Chatras, Dominique Cros:
Synthesis Method for BAW Filters Computation. 391-394 - Moustapha El Hassan
Reconfiguration of Bulk Acoustic Wave Filters: Application to WLAN 802.11b/g (2.40-2.48 GHz). 395-398 - Sandro Sawicki
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. 399-402 - Juan Núñez
Limits to a Correct Evaluation in RTD-based Ternary Inverters. 403-406 - Laurent Oyhenart, Valerie Vigneras:
Tunable photonic crystals using ferroelectric materials. 407-410 - Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten:
Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators. 411-414 - Anna Arbat, Ángel Dieguez
An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology. 415-418 - Laurent de Lamarre, Marie-Minerve Louërat, Andreas Kaiser
Optimizing Resistances and Capacitances of a Continuous-Time ΣΔ ADC. 419-422 - Arnaud Peizerat, Marc Arques, Patrick Villard, Jean-Luc Martin, Gérard Bouvier:
Pixel-level ADC by small charge quantum counting. 423-426 - Kyehyung Lee, Gabor C. Temes:
Enhanced split-architecture delta-sigma ADC. 427-430 - Mustafa Acar, Anne-Johan Annema
Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. 431-434 - Mohamed A. Elaal, Fadhel M. Ghannouchi:
ACPR Performance Study for Modified LINC Amplifier. 435-438 - Charmaine Demanuele, Ivan Grech, Joseph Micallef, Edward Gatt:
Issues on the Design of a Variable Power LINC Amplifier System in SiGe Operating at 2.4 GHz. 439-442 - Jean-François Bercher
Envelope/phase delays correction in an EER radio architecture. 443-446 - Sylvain Ranvier, Clemens Icheln
Integrated MM-Wave MIMO Antenna with Directional Diversity using MEMS Technology. 447-450 - Fouad Khelifi, Ahmed Bouridane, Fatih Kurugollu
A Robust Blind Image Watermarking Scheme in the SPIHT-Compressed Bit-Stream. 451-454 - Thomas Ea, Frédéric Amiel, Alicja Michalowska
Contribution of Custom Instructions on SoPC for iris recognition application. 455-458 - Hossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria:
A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation. 459-462 - Xin Fan, Chao Xu:
Coefficient, Pass and Code-Block Parallel Architecture for FBP Coding in JPEG2000. 463-466 - Deepak Gangadharan
Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution. 467-470 - Domenico Zito, Domenico Pepe
Modeling and Design of the CMOS Boot-Strapped Inductor for 5-6 GHz Applications. 471-474 - Hervé Leblond, Dominique Baillargeat, Pierre Blondy:
Integrated RF Devices in Suspended Technology. 475-477 - Domenico Zito, Domenico Pepe
Wide-Band Frequency-Independent Equivalent Circuit Model for Integrated Spiral Inductors in (Bi)CMOS Technology. 478-481 - Luís Mendes, João Caldinhas Vaz
Performance of Si-Integrated Wide-Band Single-Ended Switched Capacitor Arrays. 482-485 - Manuel F. M. Barros
GA-SVM Optimization Kernel applied to Analog IC Design Automation. 486-489 - Gonçalo Neves, Manuel F. M. Barros
AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow. 490-493 - Rayan Mina, Jean-Charles Grasset, Jean-François Naviner
Impact of charge injection on system-level performance of a discrete-time GSM receiver. 494-497 - Archanmael Gaillard, Régis Rogel, Samuel Crand, Taieb Mohammed-Brahim, Philippe Le Roy, Christophe Prat:
A New Active Pixel Design using μc-Si TFT Technology to Improve Brightness Uniformity of Organic Displays. 498-501 - Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi:
A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields. 502-505 - Yu Shen Lin, Damu Radhakrishnan:
Delay Efficient 32-bit Carry-Skip Adder. 506-509 - Robin Perrot, Nadine Azémard, Philippe Maurine:
Request-skip adders : CMOS standard cell data dependent adders. 510-513 - Bijoy Antony Jose, Damu Radhakrishnan:
Delay Optimized Redundant Binary Adders. 514-517 - Massimo Alioto, Gaetano Palumbo:
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders. 518-521 - Mohamad Sawan:
Implantable Smart Medical Microsystems: Limits and Challenges. 522-524 - Damien Prele
Cryogenic SiGe Hetero-Junction Bipolar Transistors From Standard Technologies For Low Noise FLL. 525-528 - Andrea Agnes, Franco Maloberti, Giuseppe Martini
Improved Chopper Stabilized Amplifier for Offset and 1/f Noise Cancellation. 529-532 - Rui Santos-Tavares
Optimum Sizing and Compensation of Two-Stage CMOS Amplifiers Based On a Time-Domain Approach. 533-536 - Kwisung Yoo, Gunhee Han, Sung Min Park:
A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications. 537-540 - Nikhil Kikkeri, Peter-Michael Seidel:
Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification. 541-544 - Konstantinos Babionitakis, George Lentaris, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Gregory Doumenis
An Efficient H.264 VLSI Advanced Video Encoder. 545-548 - Barbara Cerato, Guido Masera
A VLSI Decoder for the Golden code. 549-552 - Wei-Li Su, Herming Chiueh:
A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder. 553-556 - Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Massimo Poli:
RC-Chain: a Simple Model of Delay with a Ramp Input. 557-560 - Vincent Maingot, Régis Leveugle:
Error Detection Code Efficiency for Secure Chips. 561-564 - Mahmood Akhtar, Eliathamby Ambikairajah
A Hybrid Method for the Recognition of Acceptor Splice Sites. 565-568 - Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang:
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. 569-572 - Chiheb Rebai
Optimized Design of a Digital IQ Demodulator Suitable for Adaptive Predistortion of 3rd Generation Base Station PAs. 573-576 - Rim Barrak, Adel Ghazel, Fadhel M. Ghannouchi:
Design of Sampling-Based Downconversion Stage for Multistandard RF Subsampling Receiver. 577-580 - Mike Tempel, Georg Böck:
Shot-Noise Analysis in Circuits with Large Signal Excitations using Harmonic Balance Simulators. 581-583 - Kaushik Sengupta
Maximum frequency of operation of CMOS Static Frequency dividers: Theory and Design techniques. 584-587 - Maria Teresa Sanz
Programmable Gain Amplifiers based on High-Linearity MOS Current Dividers. 588-591 - Massimo Barbaro
Compact, low-power, analogue building blocks derived from MOSFETs translinear loops. 592-595 - Kirill Kozmin, Jonny Johansson:
Constant gm, rail-to-rail input transconductance stage with output common mode current compensation. 596-599 - Ahmed H. Madian
New 1.5-V CMOS Current Feedback Operational Amplifier. 600-603 - Arani Sinha, Shahin Nazarian, T. M. Mak:
Simulating the Effects of Process Variations on Capacitive Crosstalk. 604-607 - Mahmoud Ben Naser, Csaba Andras Moritz:
Power and Failure Analysis of CAM Cells Due to Process Variations. 608-611 - Guoyan Zhang, Ronan Farrell
An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits. 612-615 - Cheng-Cheng Yen, Ming-Dou Ker, Pi-Chia Shih:
System-Level ESD Protection Design with On-Chip Transient Detection Circuit. 616-619 - Hashem Zare-Hoseini, Izzet Kale, Richard C. S. Morling:
A Low-Power Highly Linear CMOS Transconductance Topology. 620-623 - Zhineng Zhu, Raghu Tumati, Scott D. Collins
A Low-noise Low-offset Op Amp in 0.35μm CMOS Process. 624-627 - David J. Comer, Donald T. Comer, Jonathan B. Perkins, Kevin D. Clark, Adrian P. C. Genz:
Bandwidth Extension of High-Gain CMOS Stages Using Active Negative Capacitance. 628-631 - Akram Masoom, Khayrollah Hadidi:
A 1.5-V, Constant-Gm, Rail-to-Rail Input Stage Operational Amplifier. 632-635 - Mohammed El Hassani, Delphine Rivasseau, Stéphanie Jehan-Besson
A Time-Consistent Video Segmentation Algorithm designed for Real-Time Implementation. 636-639 - M. Ben Hmida, Yousra Ben Jemaa
Fuzzy classification, image segmentation and shape analysis for Human face detection. 640-643 - Qing Pan, Guoping Yan:
Research on An Improved Anisotropic High-pass Filtering Algorithm Based on the Step Angle Searching. 644-647 - Arash Behgoo, Ali Aghagolzadeh
Unequal Error Protective and Standard Compatible Multiple Descriptions Coding for Image Communication. 648-651 - Anis Ben Aicha, Sofia Ben Jebara:
Comparison of Three Methods of Eliminating Musical Tones in Speech Denoising Subtractive Techniques. 652-655 - Peter Nilsson:
Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS. 656-659 - Cristiano Lazzari, Cristiano Santos, Ricardo Reis:
A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. 660-663 - Farah Guillot, Patrice Garcia, Mireille Mouis, Didier Belot:
Analysis of the intermodulation distortion and nonlinearity of common-base SiGeC HBTs. 664-667 - Bert Serneels, Michiel Steyaert
A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS. 668-671 - Alexandre Douyère, Jean-Daniel Lan Sun Luk, Alain Celeste, Frédéric Alicalapa:
Broadband Modelling of a High Efficiency Rectenna for Batteryless RFID Systems. 672-675 - Kamel Fezzani, Chiheb Rebai
Analysis and optimization of power line coupling circuit for CENELEC-PLC Modem. 676-679 - Matthias Frey, Hans-Andrea Loeliger, Patrick R. Merkli:
Analog Circuits for Symbol-Likelihood Computation. 680-683 - Frédéric Broydé, Evelyne Clavelier:
A Simple Method for Transmission with Reduced Crosstalk and Echo. 684-687 - Daoud Boutana
Benefits of prior speech segmentation for best time-frequency visualisation using Renyi's entropy. 688-691 - Andreas Floros, Yiorgos Tsiatouhas
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. 692-695 - Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. 696-699 - Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka:
Testing QCA Modular Logic. 700-703 - Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. 704-707 - Mitsuo Usami:
Ultra-Small RLID Chip Technology. 708-711 - Stefan Mendel, Christian Vogel
A Compensation Method for Magnitude Response Mismatches in Two-channel Time-interleaved Analog-to-Digital Converters. 712-715 - Luis Hernández, Enrique Prefasi
Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder. 716-719 - Alessandro Cabrini, Andrea Fantini, Guido Torelli:
High-Efficiency Regulated Charge Pump for Non-Volatile Memories. 720-723 - Laura Gobbi, Alessandro Cabrini, Guido Torelli:
High-Efficiency CMOS Charge Pump. 724-727 - Charlène Goudemand, Marc Georges Gazalet, François-Xavier Coudoux, Patrick Corlay, Mohamed Gharbi
Reduced Complexity Power Minimization Algorithm for DMT Transmission - Application to Layered Multimedia Services over DSL. 728-731 - Siamak Yousefi, Hamid Reza Rabiee
Improving the Security of the Shi Reversible Data Hiding Algorithm. 732-735 - Ehsan Kamrani
Teleoperation via Internet with Time-Varying Delay. 736-739 - Jeedella S. Jeedella, Hussain Al-Ahmad
Improved Transient Frequency Response of IIR Filters with Multiple Frequency Initialization. 740-743 - Xiaofeng Wu, Zi Qiang Lang, Stephen A. Billings:
Output Frequencies of A Class of Nonlinear Systems. 744-747 - Levent Aksoy
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. 748-751 - Péter Szántó, Béla Fehér, Gábor Szedö:
High Performance Timing-Driven Rank Filter. 752-755 - David Castells-Rufas
Camera-based Digit Recognition System. 756-759 - Graeme Kelly, Robin Woodburn, Ian Underwood, Dwayne Bums, Roger Monteith:
A Full-Color QVGA Microdisplay using Light-Emitting-Polymer on CMOS. 760-763 - Yusuke Yachide, Makoto Ikeda, Kunihiro Asada:
High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine. 764-767 - Fang-Ju Lin, Herming Chiueh:
A Micro-architecture Simulator for Multimedia Stream Processor. 768-771 - Bilel Belhadj Mohamed, Chiheb Rebai
Intra- and Inter-Processors Memory Size Estimation for Multithreaded MPSoC Modeled in Simulink. 772-775 - Romain Vaslin, Guy Gogniat
Trusted computing - A new challenge for embedded systems. 776-779 - Hanene Ben Fradj, Cécile Belleudy, Michel Auguin, Alain Pegatoquet:
Multi-Bank Memory Allocation for Multimedia Application. 780-783 - Bertrand Le Gal, Emmanuel Casseau:
IP Generation Targeting Multiple Bit-Width Standards. 784-787 - Dominique Morche, Frédéric Hameau, David Lachartre, Gilles Masson, Christopher Mounet, Michaël Pelissier, Didier Helal, Lydi Smaini, Didier Belot:
Digital Radio Front-End for High Data Rate Impulse UWB System. 788-791 - Thierry Taris, Ouail El-Gharniti, Jean-Baptiste Bégueret, Eric Kerherve
UWB LNAs using LC ladder and transformers for input matching networks. 792-796 - John F. M. Gerrits, John R. Farserotu, John R. Long:
FM-UWB: A Low-Complexity Constant Envelope LDR UWB Approach. 797-801 - Philippe Lombard, Emilie Ponthus, Emil Novakov, Jean-Michel Fournier:
Effect of RF Front-End Parameters on UWB-OFDM Receiver Performances in Presence of Adjacent Channel Interferers. 802-805 - V. S. Sheeba, Elizabeth Elias:
Two-Dimensional FIR Signal Adapted Filter Banks. 806-809 - Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras:
A High Performance VLSI FFT Architecture. 810-813 - Ahmed Ben Atitallah
An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA. 814-817 - Yngvar Berg, Omid Mirmotahari
Ultra low voltage CMOS gates. 818-821 - Vassilios A. Chouliaras, Konstantia Koutsomyti, Tom R. Jacobs, Simon Parr, David J. Mulvaney, Robert Thomson:
SystemC-defined SIMD instructions for high performance SoC architectures. 822-825 - Ji Hwan Park, Hee Ju Park, Jeong Hun Kim, Kyu-sam Lim, Suki Kim:
Architecture of an Efficient Area and Flexible Multi-CODEC Processor. 826-829 - Sergio Saponara
Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier. 830-833 - Pawel Biernacki
Strategies for adaptive nonlinear noise reduction Volterra-Wiener filter structure selection. 834-837 - Jeong Beom Kim, Sun Hong Ahn:
An 11Gb/s CMOS Demultiplexer Using Redundant Multi-valued Logic. 838-841 - Somayyeh Rahimian Omam, S. M. Mortazavi Zanjani, Sied Mehdi Fakhraie, Omid Shoaei
Implementation of Multiplier Block with Reduced Adder Cost. 842-845 - Stefania Perri
SAD-Based Stereo Matching Circuit for FPGAs. 846-849 - Marie Ramon, François-Xavier Coudoux, Marc Gazalet, Mohamed Gharbi
Systematic Lossy Error Protection of Video based on Reduced Spatial Resolution. 850-853 - Usman Ali, Syed Junaid Nawaz, Nazish Jawad:
A Real-time Control System for Home/Office appliances automation, from mobile device through GPRS network. 854-857 - Hang Wang, Zanji Wang, Jingbo Guo:
Performance of DSSS against Repeater Jamming. 858-861 - Minghua Shi, Amine Bermak
Committee Machine with Over 95% Classification Accuracy for Combustible Gas Identification. 862-865 - José Luis Ayala, Cándido Méndez, Marisa López-Vallejo
Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors. 866-869 - Abdellaoui Mehrez
Hybrid method for cereal grain identification using morphological and color features. 870-873 - Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen:
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. 874-877 - Jan Schat:
Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. 878-881 - Giuseppe Di Cataldo, Rosario Mita, Gaetano Palumbo, Melita Pennisi:
Modeling of Feedback Analog Circuits with VHDL. 882-885 - Kyu-sam Lim, Hwangyoung So, Sejin Kang, Jeong Hun Kim, Suki Kim:
3 Megapixel Camera Signal Processor for Mobile Camera Applications. 886-889 - Ming-Chung Lee, Herming Chiueh:
An Implementation of Integrable Low Power Techniques for Modern Cell-Based VLSI Designs. 890-893 - Huabiao Qin, Fei Wang:
Modeling of Operational Amplifier based on VHDL-AMS. 894-897 - Erik Backenius, Mark Vesterbacka:
Effect of Simultaneous Switching Noise on an Analog Filter. 898-901 - Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo:
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. 902-905 - Robert Suszynski, Krzysztof Wawryn:
FPAA Prototyping of ΣΔ Analog Digital Converters. 906-909 - Byoung-Il Kim, Wan-Gyu Lee, Hak-Choong Kim, Jae-Sik Lee, Tae-Gyu Chang:
Implementation of a Mixed Signal Chip for Multichannel Audio Equalizer with Sigma-delta A/D Conversion. 910-913 - Shahram Mohammad Nejad, Saeed Olyaee
Accuracy Improvement by Nonlinearity Reduction in Two-Frequency Laser Heterodyne Interferometer. 914-917 - Shahram Mohammad Nejad, Maryam Pourmahyabadi, Ali Asghar Amidian:
Optimal Dark Current Reduction in Quantum Well 9 μm GaAs/AlGaAs Infrared Photodetectors With Improved Detectivity. 918-921 - Laurent Gatet, Hélène Tap-Béteille, Marc Lescure:
Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal Processing. 922-925 - Nicolás Medrano, Maria Teresa Sanz
An Analog-Digital Neural Processor for Integrated Sensor Conditioning. 926-929 - Jinxiang Yang, Shouming Zhong, Xingwen Liu:
Exponential Stability for Cellular Neural Networks with Delay. 930-933 - José María Granado Criado
Using FPGAs to Implement Artificial Neural Networks. 934-937 - Lourdes Miro-Amarante
A LVDS Serial AER Link. 938-941 - Mohamed Krid
FPGA Implementation of Programmable Pulse Mode Neural Network with on Chip Learning for signature application. 942-945 - Jean Tomas, Yannick Bornat
Design of a modular and mixed neuromimetic ASIC. 946-949 - Raf Schoofs, Tom Eeckelaert, Michiel Steyaert
A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology. 950-953 - Manuel Sanchez-Renedo, Susana Patón
A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. 954-957 - Carmine Ciofi, Graziella Scandurra
On the calibration of AD and DA converters based on R/�?R ladder networks. 958-961 - Nejmeddine Jouida, Chiheb Rebai
Continuous-Time Complex Bandpass Modulator: Key Component for Highly Digitized Receiver. 962-965 - Umut Yazkurt, Günhan Dündar
Scaling Input Signal Swings of Overloaded Integrators in Resonator-based Sigma-Delta Modulators. 966-969 - Faouzi Zarai
Secured and Seamless Handoff in Wireless Fourth Generation Systems. 970-973 - Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Javier Casajús-Quirós:
Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver. 974-977 - David Bueche, Patrick Corlay, Marc Gazalet, François-Xavier Coudoux, Marc Slachciak:
On the Use of a Performance Indicator for Optimal Pilot Positioning in Multicarrier Systems. 978-981 - Guilleminot Celine, Laurent Andrieux:
Telecommunication synchronisation developpement based on high level virtual prototype. 982-985 - Marina M. Marjanovic, José Manuel Páez-Borrallo:
A Low Complexity Simulation Algorithm for TH-UWB MMSE RAKE Receiver in NLOS Channel. 986-990 - Stephane Thuries, Eric Tournier, Jacques Graffeuil:
A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe: C Technology. 991-994 - Gérald Arnould, Fabrice Monteiro, Abbas Dandache:
A Digital Frequency Shift Keying Demodulator. 995-998 - Anouar Benchahed, Adel Ghazel, Mohamed Mabrouk, Chiheb Rebai
RF Digital Predistorter for Power Amplifiers of 3G Base Stations. 999-1002 - Sanjeev Manandhar, Steven Eugene Turner, David E. Kotecki
A 20-GHz and 46-GHz, 32x6-bit ROM for DDS Application in InP DHBT Technology. 1003-1006 - Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. 1007-1010 - Sébastien Chartier, Bernd Schleicher
79 GHz Fully Integrated Fully Differential Si/SiGe HBT Amplifier for Automotive Radar Applications. 1011-1014 - Andrea Bevilacqua
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection. 1015-1018 - Thierry Taris, Nicolas Seller, Romaric Toupe, Hervé Lapuyade, Jean-Baptiste Bégueret, Yann Deval
A 4mA, 0.25 SiGe, 23GHz BiFET Low Noise Amplifier. 1019-1022 - Meik Huber, Stefan von der Mark, Georg Böck:
A Dual Stage GaAs Amplifier for a K-Band Direct Receiver. 1023-1025 - Yang Chuan Chen, Chun-Hsing Li, J. K. Huang, Chien-Nan Kuo, Yu Ting Cheng:
Low Power 38-GHz UWB Tunable LNA Design Using SiP Technology. 1026-1029 - Fabien Prégaldiny, Jean-Baptiste Kammerer, Christophe Lallement
Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design. 1030-1033 - Antoine Jalabert, Fabien Clermidy, Amara Amara:
A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors. 1034-1037 - Sylvain Giraud, Stephane Bila
3D simulation of thin-film bulk acoustic wave resonators (FBAR). 1038-1041 - Alexandre A. Shirakawa, Jean-Marie Pham, Pierre Jarry, Eric Kerhervé
An Improved Isolation W-CDMA Ladder BAW-SMR Filter. 1042-1044 - Matthieu Desvergne, Carolynn Bernier
Intermediate Frequency Lamb Wave Resonators and Filters for RF Receiver Architectures. 1045-1048 - David Bol, Jean-Didier Legat, José M. Quintana
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. 1049-1052 - Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada:
Pre-conditioning Free Footless DCVSL for High-performance Datapaths. 1053-1056 - Reginaldo Tavares, Cristina Meinhardt
orBDDs Direct Mapping for Structured Logic Circuits. 1057-1060 - Jingye Xu, Masud H. Chowdhury:
Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining. 1061-1064 - Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada:
Exact Minimum Logic Factoring via Quantified Boolean Satisfiability. 1065-1068 - Reza Hashemian:
Designing Analog Circuits with Reduced Biasing Power. 1069-1072 - Cristiano Azzolini, Andrea Boni:
BiCMOS vs. CMOS Operational Amplifiers for High-Speed Pipelined A/D Converters. 1073-1076 - Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi, Hajime Shibata:
Frequency Response Analysis of Latch Utilized in High-Speed Comparator. 1077-1080 - Apostolos P. Fournaris, Odysseas G. Koufopavlou:
A Systolic Inversion Architecture Based on Modified Extended Euclidean Algorithm for GF(2K) Fields. 1081-1084 - Ting Liu, Camel Tanougast
Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system. 1085-1088 - George N. Selimis, Apostolos P. Fournaris, Odysseas G. Koufopavlou:
Applying Low Power Techniques in AES MixColumn/InvMixColumn Transformations. 1089-1092 - Koji Inoue:
Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache. 1093-1096 - Maher Jridi, Guillaume Monnerie, Lilian Bossuet, Dominique Dallet:
An offset and gain calibration method for time-interleaved analog to digital converters. 1097-1100 - Bo Fu, Paul Ampadu:
Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing. 1101-1104 - Constantin Paleologu, Andrei Alexandru Enescu, Silviu Ciochina:
Recursive Least-Squares Lattice Adaptive Algorithm Suitable for Fixed-Point Implementation. 1105-1108 - Navid Zeraatkar
Implementation and Synthesis of a Sorting Network. 1109-1112 - Antoine Frappé
Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters. 1113-1116 - Nejdat Demirel, Eric Kerhervé
A Study of High-Frequency Bandpass Delta-Sigma Transmitter Architectures. 1117-1120 - Hassène Mnif, Mourad Fakhfakh, Ibtihel Krout, M. Barhoumi, Mourad Loulou:
A ΣΔ fractional- N synthesizer for GSM standard specifications. 1121-1124 - James Wei, Dominique Morche, Serge Ramet, Jacques Verdier:
A Programmable Complex FIR Filter with Integrated MEMS Filter for Front-end Charge Sampling Receiver. 1125-1128 - Duncan L. MacFarlane, Jian Tong, Robert Hunt, Issa M. S. Panahi, Kent Wade:
Direct Form I Active Optical Filters Realized in an Integrated Photonic Architecture. 1129-1132 - Estelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger:
A 100dB dynamic range CMOS image sensor with global shutter. 1133-1136 - Jae Kwan Kwon, Wonseok Oh, Jongchan Choi, Jung-Won Han, Boo-Young Choi, Sung Min Park:
A 1Gb/s 4-Channel Optical Transceiver Chipset for Automotive Wired Networks. 1137-1139 - Chi Ho Hwang, Yong Soo Lee, Hee Chul Lee:
High-Performance Pixelwise Readout Integrated Circuits for Microbolometer. 1140-1143 - João Paulo Carmo
Low-power 2.4-GHz RF transceiver for wireless EEG module plug-and-play. 1144-1147 - Sébastien Heini, Christine Hu-Guo, Marc Winter, Yann Hu:
A New PhotoFET for Monolithic Active Pixel Sensors Using CMOS Submicronic Technology. 1148-1151 - Yaser M. A. Khalifa, Ehi Okoene, Mohamed Basel Al-Mourad:
A Comparison between Centerlized and Distributed agent-based Evolutionary Target Tracking System. 1152-1155 - Koen Cornelissens, Michiel Steyaert
A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC. 1156-1159 - Adam Strak, Hannu Tenhunen:
Investigation of Timing Jitter in NAND and NOR Gates Induced by Power-Supply Noise. 1160-1163 - Fernando Paixão Cortes, Alessandro Girardi
Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization. 1164-1167 - Amir Ghaffari, Adib Abrishamifar:
A Wide-Range Delay-Locked Loop with a New Lock-Detect Circuit. 1168-1171 - Yaseer Arafat Durrani, Teresa Riesgo:
Power Macromodeling for IP Modules. 1172-1175 - Mathieu Dubois, El Mostapha Aboulhamid, Frédéric Rousseau:
Acceleration for a compiled Transaction Level Modeling simulation. 1176-1179 - Harris E. Michail, Athanasios P. Kakarountas
Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core. 1180-1183 - Safa Chouchane, Hassani Messaoud:
Pole optimisation of GOB-Volterra model for non linear MISO system. 1184-1187 - Dionysios I. Reisis, Nikolaos Vlassopoulos:
Address Generation Techniques for Conflict Free Parallel Memory Accessing in FFT Architectures. 1188-1191 - Qiaoyan Yu, Paul Ampadu:
Cell Ratio Bounds for Reliable SRAM Operation. 1192-1195 - Pedro Echeverría, José Luis Ayala, Marisa López-Vallejo
Leakage Energy Reduction in Banked Content Addressable Memories. 1196-1199 - Mohammad Gh. Mohammad
Switched Polarity Charge Pump for NOR-type Flash Memories. 1200-1203 - Thomas M. McCoy, Paul V. Brennan, Richard J. Bullock:
An RF-ID Receiver Using SAW Filters For Wideband Synchronisation. 1204-1207 - Vincent Cheynet de Beaupré, Lakhdar Zaïd, Wenceslas Rahajandraibe, Gilles Bas:
A Fully Integrated 2.45-GHz Frequency Synthesizer and FSK Modulator. 1208-1211 - Alexandre Serres, Yvan Duroc, Tan-Phu Vuong, José Ewerton P. de Farias, Glauco Fontgalland:
A New Simple UWB Monocycle Pulse Generator. 1212-1215 - Mehdi Salehi, Abdolreza Nabavi, Nader Ghadimi:
A Low-Power High-Rate Modulator for Ultra-Wideband Transmitters. 1216-1219 - Yuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Ching-Ta Chen:
A Pre-processing Based Real-Time Address Tracer for Embedded Microprocessors. 1220-1223 - Tommaso Addabbo
Efficient Post-Processing Module for a Chaos-based Random Bit Generator. 1224-1227 - Francisco Fons, Mariano Fons, Enrique Cantó
Hardware-Software Co-design of a Dynamically Reconfigurable FPGA-based Fuzzy Logic Controller. 1228-1231 - Samuel Charbouillot, Annie Pérez, Daniele Fronte:
A Programmable Hardware Cellular Automaton : Example of Data Flow Transformation. 1232-1235 - Michel Nowak, Nicolas Delorme, François Conseil, Gilles Jacquemod:
A novel architecture for remote interrogation of wireless battery-free capacitive sensors. 1236-1239 - Cedric Rechatin, Patrick Audebert, Nacer Abouchi, Jean-Marc Galvan:
A new Polysilicon TFT capacitive fingerprint sensor with advanced mismatch compensation. 1240-1243 - Jorge Portilla
A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks. 1244-1247 - José A. Afonso
MAC Protocol for Low-Power Real-Time Wireless Sensing and Actuation. 1248-1251 - Igor M. Filanovsky, Chris J. M. Verhoeven:
On Stability of Synchronized van der Pol Oscillators. 1252-1255 - Raúl Regidor, Roberto Esper-Chaín, Félix Tobajas
A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology. 1256-1259 - Jordi Bonet-Dalmau
Detailed Solution Curves and Bifurcation Boundaries of the Forced van der Pol Oscillator. 1260-1263 - Takeshi Shima:
Application of the inductor multiplier. 1264-1267 - Samir Ben Salem, Dorra Sellami Masmoudi, Ashwek Ben Said, Mourad Loulou:
An optimized low voltage and High Frequency CCII based multifunction Filters. 1268-1271 - Ludovic Apvrille, Muhammad Waseem
A UML-based Environment for System Design Space Exploration. 1272-1275 - Minghua Shi, Amine Bermak
An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier Using Distributed Arithmetic. 1276-1279 - Miguel Eduardo Litvin, Samiha Mourad, William Terry, Janice Terry:
Wave Pipelining using Self Reset Logic. 1280-1283 - Chuan-Sheng Lin, Kuang-Yuan Chen, Yu-Hsian Wang, Lan-Rong Dung:
A NAND Flash Memory Controller for SD/MMC Flash Memory Card. 1284-1287 - Huynh Trong Anh, Jinsang Kim, Won-Kyung Cho, Jongchan Choi:
An Efficient Hardware Implementation of a Robust and Low-Complexity ADSRC Timing Synchronization Design. 1288-1291 - Rubil Ahmadi:
A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay. 1292-1295 - Jon Alfredsson, Bengt Oelmann:
Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating Gate Designs. 1296-1299 - Senthil Jayapal, Yiannos Manoli:
Precharge Node based Variable Forward Body Bias for Low-Energy LSIs. 1300-1303 - Stefano Chinnici, Carmelo Decanis:
Design of a flexible low-power modem chip for point to point radio link cellular backhaul applications. 1304-1307 - Massimo Alioto, Rosario Mita, Gaetano Palumbo:
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers. 1308-1311 - Domenico Zito, Domenico Pepe
Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Applications. 1312-1315 - Kamel Haddadi, Hassan El Aabbaoui, Christophe Loyez
Wide-band 0.9 GHz to 4 GHz Four-Port Receiver. 1316-1319 - Delia Rodríguez de Llera Gonzalez, Ana Rusu
Automated Design of a WCDMA/WLAN Multi-standard Receiver. 1320-1323 - Rim Barrak, Mounira Msehli, Adel Ghazel, Ammar Kouki:
Optimized AIS/DSC homodyne receiver design. 1324-1327 - Chung-Yu Wu, Yi-Kai Lo, Min-Chiao Chen:
A 3.110.6 GHz CMOS Direct-Conversion Receiver for UWB Applications. 1328-1331 - Carlos Manuel Domínguez-Matas, Ricardo Carmona-Galán
Robust Symmetric Multiplication for Programmable Analog VLSI Array Processing. 1332-1335 - Mehdi Aghagolzadeh, Hamid Soltanian-Zadeh
Finding the Number of Clusters in a Dataset Using an Information Theoretic Hierarchical Algorithm. 1336-1339 - Mark Bonnici, Edward Gatt, Joseph Micallef, Ivan Grech:
Artificial Neural Network Optimization for FPGA. 1340-1343 - Jayawan H. B. Wijekoon
Simple Analogue VLSI Circuit of a Cortical Neuron. 1344-1347 - P. W. Chandana Prasad, Ashutosh Kumar Singh
Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network. 1348-1351 - Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod:
Scalable Model for Multi-Standard Phase Locked Loop. 1352-1355 - Monica Figueiredo
Noise and Jitter in CMOS Digitally Controlled Delay Lines. 1356-1359 - Saeed Olyaee
Frequency-Path Modeling for Three-Longitudinal-Mode Interferometer. 1360-1363 - Jin-Tai Yan
Area-Driven White Space Distribution for Detailed Floorplan Design. 1364-1367 - Cristina Della Fiore, Franco Maloberti, Miguel G. Andrale:
Dynamic Element Matching for Low-power ΣΔModulator with R-C based internal DAC. 1368-1371
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:03 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: