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ISCAS 1995: Seattle, WA, USA - Volume 1
- 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995. IEEE 1995, ISBN 0-7803-2570-2
Delta-Sigma Techniques I
- Walt T. Bax, Tom A. D. Riley, Calvin Plett, Miles A. Copeland:
A Sigma-Delta Frequency Discriminator Based Synthesizer. 1-4 - Ian Galton:
A Practical Second-Order Delta-Digma Frequency-to-Digital Converter. 5-8 - Peicheng Ju, Ken Suyama, Paul F. Ferguson Jr., Wai Lee:
A Highly Linear Switched-Capacitor DAC for Multi-Bit Sigma-Delta D/A Applications. 9-12 - Rex T. Baird, Terri S. Fiez:
Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. 13-16 - Mervyn H. Adams, Chris Toumazou:
A Novel Architecture for Reducing the Sensitivity of Multibit Sigma-Delta ADCs To DAC Nonlinearity. 17-20
VLSI Circuits I
- Anura P. Jayasumana, Yashwant K. Malaiya, Sankaran M. Menon:
A Novel High-Speed BiCMOS Domino Logic Family. 21-24 - Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng:
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. 25-28 - José Antonio Hidalgo López, Juan Carlos Tejero-Calado, José Fernández Ramos, Alfonso Gago Bohórquez:
New Types of Digital Comparators. 29-32 - Richard X. Gu, Mohamed I. Elmasry:
Power Dissipation in Deep Submicron CMOS Digital Circuits. 33-36 - Stefan A. Kühn, Michael B. Kleiner, Roland Thewes, Werner Weber:
Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Capacitive Coupling. 37-40
Floorplanning and Module Generation
- Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman:
Floorplanning with Datapath Optimization. 41-44 - Kai-Yuan Chao, D. F. Wong
:
Floorplanning for Low Power Designs. 45-48 - Morteza Saheb Zamani, Graham R. Hellestrand:
A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. 49-52 - Piyush K. Sancheti, Sachin S. Sapatnekar:
Layout Optimization Using Arbitrarily High Degree Posynomial Models. 53-56 - Wei-Liang Lin, Majid Sarrafzadeh:
A Linear Arrangement Problem with Applications. 57-60
Novel IIR and FIR Implementations I
- A. Tawfik, Panajotis Agathoklis, Fayez El Guibaly:
New IIR Digital Filter Realizations Using Residue-Feedback. 61-64 - Svante Signell, Todor G. Kouyoumdjiev, Kåre Mossberg, Lennart Harnefors:
Design of Bilinear Digital Ladder Filters. 65-68 - Svante Signell, Lennart Harnefors:
Analysis of Bilinear Digital Ladder Filters. 69-72 - Kasyapa Balemarthy, Steven C. Bass:
General, Linear Boundary Conditions in MD Wave Digital Simulations. 73-76 - Jin-Gyun Chung, Keshab K. Parhi
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain. 77-80
Wideband Communication
- XuDuan Lin, KyungHi Chang, Jaeseok Kim:
Optimal PN Sequences Design for Quasi-Synchronous CDMA Communication Systems. 81-84 - C. A. Carty, Mohsin M. Jamali, A. G. Eldin, Subhash C. Kwatra, R. E. Jones:
A High Speed 800 Channel Digital Interpolator Network. 85-88 - S. Subramanian, Dale J. Shpak, Andreas Antoniou:
Performance of a Quasi-Newton Adaptive Filtering Algorithm for a CDMA Indoor Wireless System. 89-92 - Nabil Abd Rabou, Hiroaki Ikeda, Hirofumi Yoshida:
Wideband Optical Fiber Signal Transmission System of 300MHz Bandwidth Using LED. 93-96 - Norman M. Filiol, Calvin Plett, Tom A. D. Riley, Miles A. Copeland:
Bit-Error Rate Measurements for A High Frequency Interpolated Frequency-Hopping Spread-Spectrum System. 97-100
Existence, Uniqueness and Stability of DC Operating Points
- Arturo Sarmiento-Reyes:
A Novel Method to Predict Both, the Upper Bound on the Number and the Stability of DC Operating Points of Transistor Circuits. 101-104 - Michael M. Green:
A Method for Identifying Combinations of Transistors that can be Replaced with a Single Transistor when Applying the Nielsen-Willson Theorem. 105-108 - Robert M. Fox:
Design-Oriented Analysis of CD Operating-Point Instability. 109-112 - Shek-Wai Ng, Yim-Shu Lee, C. K. Tse, Simon C. Wong:
Stability of a Circuit with Parasitic Capacitances. 113-116 - Michael M. Green, Robert C. Melville:
Sufficient Conditions for Finding Multiple Operating Points for CD Circuits Using Continuation Methods. 117-120
Learning in Neural Networks
- Syozo Yasui, Aleksander Malinowski
Convergence Suppression and Divergence Facilitation: New Approach to Prune Hidden Layer and Weights of Feedforward Neural Networks. 121-124 - Juan Seijas, José L. Sanz-González:
Basic-Evolutive Algorithms for Neural Networks Architecture Configuration and Training. 125-130 - Aleksander Malinowski, Tomasz J. Cholewo, Jacek M. Zurada:
Capabilities and Limitations of Feedforward Neural Networks with Multilevel Neurons. 131-134 - Ruey-Wen Liu, Yih-Fang Huang, Xie-Ting Ling:
A Novel Approach to the Convergence of Unsupervised Learning Algorithms. 135-138 - Clifford Sze-Tsan Choy, Pui-Kin Ser, Wan-Chi Siu:
Peak Detection in Hough Transform Via Self-Organizing Learning. 139-143
Global Bifurcations and Complex Nonlinear Phenomena in the Power System I
- Mohamed Belkhayat, Roger E. Cooley, Eyad H. Abed:
Stability and Dynamics of Power Systems with Regulated Converters. 143-145 - X. Jiang, Heinz Schättler, John Zaborszky, Vaithianathan Venkatasubramanian:
Hard Limit Induced Oscillations. 146-150 - M. A. Pai, Mark Laufenberg:
On the Computation of Hetero Clinic Orbits in Dynamical Systems. 151-154
Combinatronics in Advanced CAS I
- Toshiya Mashima, Toshimasa Watanabe:
Approximation Algorithms for the k-Edge-Connectivity Augmentation Problem. 155-158 - Hiroshi Tamura, Ryohei Sato, Masakazu Sengoku, Shoji Shinoda, Takeo Abe:
The Structure of Networks Realized from Terminal Capacity Matrices. 159-162 - Gustavo E. Téllez, Majid Sarrafzadeh:
On Rectilinear Distance-Preserving Trees. 163-166 - Kai Wang, Wai-Kai Chen:
Floorplan Area Optimization Using Network Analogous Approach. 167-170
Delta-Sigma Techniques II
- Omid Shoaei, W. Martin Snelgrove:
A Multi-Feedback Design for LC Bandpass Delta-Sigma Modulators. 171-174 - Mats Erling Høvin, Alf Olsen, Tor Sverre Lande, Chris Toumazou:
Delta-Sigma Converters Using Frequency-Modulated Intermediate Values. 175-178 - Huibert-Jan Verhoeven, Johan H. Huijsing:
Design of Thermal Sigma-Delta Modulators for Smart Thermal Sensors. 179-182 - Rohit Mittal, David J. Allstot:
Low-Power High-Speed Continuous-Time Sigma-Delta Modulators. 183-186
VLSI Clocking Circuits
- Mehmet Soyuer, Herschel A. Ainspan, John F. Ewen:
A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery. 187-190 - Fuminori Kobayashi, Masayuki Haratsu:
A Digital PLL with Finite Impulse Responses. 191-194 - Patrik Larsson:
A Wide-Range Progammable High-Speed CMOS Frequency Divider. 195-198 - Jiin-Chuan Wu, Hun-Hsien Chang:
A 550MHz 9.3mW CMOS Frequency Divider. 199-202
Performance-Driven Routing
- Jason Cong, Patrick H. Madden:
Performance Driven Routing with Mulitiple Sources. 203-206 - Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. 207-210 - Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida:
An MCM Routing Algorithm Considering Crosstalk. 211-214 - Jason Cong, Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing. 215-218
Novel IIR and FIR Implementations II
- Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal:
DSP Implememntation of Fast FIR Filtering Algorithms Using Short FFT's. 219-222 - Chao-Liang Chen, Kei-Yong Khoo, Alan N. Willson Jr.:
An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. 223-226 - Mitsuhiko Yagyu, Toshiyuki Yoshida, Akinori Nishihara, Nobuo Fujii:
Design of FIR Digital Filters with Minimum Weight Representation. 227-230 - Darren N. Pearson, Keshab K. Parhi
Low-Power FIR Digital Filter Architectures. 231-234
Image Processing and Compression
- Tak Po Chan, Bing Zeng, Ming L. Liou:
Visual Pattern BTC with Two Principle Colors for Color Images. 235-238 - Andrea Maccato, Rui J. P. de Figueiredo:
The Image and Associated Orientation Signatures. 239-242 - W. K. Lam, C. K. Li:
Classification of Rotated and Scaled Textures by Local Linear Operations. 243-246 - Halûk Aydinoglu, Monson H. Hayes:
Stereo Image Coding. 247-250
Aspects of Chaos
- Marco Gilli:
A Spectral Approach for Studying Spatio-Temporal Chaos. 251-254 - L. M. Khadra, T. J. Maayah, M. Vinson, H. Dichhauss:
Chaos Detection in Time Series: A Statistical Approach. 255-258 - Kunihiko Mitsubori, Toshimichi Saito:
A Hysteresis Hyperchaos Generator Family. 259-262 - Hisa-Aki Tanaka, Kazuo Horiuchi, Shin'ichi Oishi:
Chaos from Orbit-Flip Homoclinic Orbits Generated in Real Systems. 263-266
Implementation of Neural and Fuzzy Circuits
- Michael Scholles, Bedrich J. Hosticka, Markus Schwarz:
Real-Time Application of Biology-Inspired Neural Networks Using and Emulator with Dedicated Communication Hardware. 267-270 - Ammar B. A. Gharbi, Fathi M. A. Salam:
Implementation and Test Results of a Chip for the Separation of Mixed Signals. 271-274 - Jaime Ramírez-Angulo:
A BiCMOS Universal Membership Function Circuit with Fully Independant, Adjustable Parameters. 275-278 - Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo:
A Circuit for Learning in Fuzzy Logic-Based Controllers. 279-286
Global Bifurcations and Voltage Stability Phenomena in Electric Power Systems I
- Chia-Chi Chu
An Investigation of Invariant Properties of Unstable Equilibrium Points on the Stability Boundary for Simple Power System Models. 287-290 - Rajesh Rajaraman, Ian Dobson:
Damping and Incremental Energy in Thyristor Switching Circuits. 291-294
Analog Circuits and Signal Processing
- Chung-Yu Wu, Heng-Shou Hsu:
The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters. 295-298 - Reinoud F. Wolffenbuttel, Ger de Graaf, E. Engen:
Bipolar Circuits for Readout of an Integrated Silicon Color Sensor. 299-302 - Erik Bruun
Bandwidth Limitations in Current Mode and Volage Mode Integrated Feedback Amplifiers. 303-306 - Chiu-sing Choy, Cheong-Fat Chan, M. H. Ku:
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. 307-310 - D. Perry, Gordon W. Roberts:
Log-Domain Filters Based on LC Ladder Synthesis. 311-314 - Giuseppe Di Cataldo, Giuseppe Palmisano, Gaetano Palumbo:
A CMOS CCII+. 315-318 - Feng Wang, Ramesh Harjani:
Dynamic Amplifiers: Settling, Slewing and Power Issues. 319-322 - Peter Shah, Chris Toumazou:
A New BiCMOS Technique for Very Fast Discrete-Time Signal Processing. 323-326
Digital Signal Processing
- Roberto Manduchi:
2-D IFIR Structures Using Generalized Factorable Filters. 327-330 - Pavel Zahradnik, Rolf Unbehauen:
Frequency Shift of Two-Dimensional Real Coefficient Zero Phase Fir Digital Filters. 331-334 - Srikanth Pokala, Arnab K. Shaw:
Optimal spatial-domain design of 2-D IIR filters. 335-338 - H. Safiri, Majid Ahmadi, V. Ramachandran:
Design of 2-Dimensional Digital Filters Using 2-D All-Pass Building Blocks. 340-343 - Rajamohana Hegde, B. A. Shenoi:
Design of 2-D IIR Filters Using a New Digital Spectral Transformation. 344-347 - Takao Hinamoto, Shuji Karino, Naoki Kuroda:
Error Spectrum Shaping in 2-D Digital Filters. 348-351 - Haiyun Luo, Songwu Lu, Andreas Antoniou:
New Algorithm for Structurally Balanced Model Reduction of 2-D Discrete Systems. 352-355 - Haiyun Luo, Songwu Lu, Andreas Antoniou:
A Weighted Balanced Realization of 2-D Discrete Systems. 357-360 - Vesa Välimäki:
A New Filter Implementation Strategy for Lagrange Interpolation. 361-364 - Miki Haseyama, Tohru Hirohku, Hideo Kitajima:
A Realization Method of an ARMAX Lattice Filter. 365-368
VLSI CAD
- Alexander Y. Tetelbaum:
Path Search for Complicated Functions. 369-372 - Carsten F. Ball, Andreas Just, Dieter A. Mlynski:
A Fuzzy Mean Field Approach for Partitioning and Placement. 373-376 - Bernhard M. Riess, Gisela G. Ettelt:
Speed: Fast and Efficient Timing Driven Placement. 377-380 - Xiao Quan Li, Marwan A. Jabri:
Neural Network Based Estimation of VLSI Building Block Dimensions from Schematic. 381-384 - M. Kemal Unaltuna, Vijay Pitchumani:
ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. 385-388 - Ian M. Bell, Kevin R. Eckersall, Stephen J. Spinks, Gaynor E. Taylor:
Fault Orientated Test and Fault Simulation of Mixed Signal Integrated Circuits. 389-392 - Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). 393-396
VLSI Applications and Neural Networks
- Stefan Wolter, Holger Matz, Andreas Schubert, Rainer Laur:
On the VLSI Implementation of the International Data Encryption Algorithm IDEA. 397-400 - William A. Chren Jr.:
One-Hot Residue Coding for High-Speed Non-Uniform Pseudo-Random Test Pattern Generation. 401-404 - Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. 405-408 - Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee:
A New Architecture for Analog Boundary Scan. 409-412 - Jörg Kramer, Rahul Sarpeshkar, Christof Koch:
An Analog VLSI Velocity Sensor. 413-416 - Mario Salerno, F. Sargeni, V. Bonaiuto:
DPCNN: A Modular Chip for Large CNN Arrays. 417-420 - Chua-Chin Wang, Jeng-Ming Wu:
Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. 421-424 - Baoyun Wang, Luxi Yang, Hongtao Lu, Zhenya He:
On the Capacity of Intraconnected Bidirectional Associative Memory. 425-428 - Yoshihiko Horio, Ken Suyama:
Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. 429-432
Video Coding and Processing
- Michael C. Doggett, Graham R. Hellestrand:
A Hardware Architecture for Video Rate Shading of Volume Data. 433-436 - Bin Fu, Keshab K. Parhi
Generalized Multiplication Free Arithmetic Codes. 437-440 - Hugh Q. Cao, Weiping Li:
A New Multilevel Codebook Searching Algorithm for Vector Quantization. 441-444 - A. Nabout, Bing Su, Hassan A. Nour Eldin:
A Novel Closed Contour Extractor, Principle and Algorithm. 445-448 - Yui-Lam Chan, Wan-Chi Siu:
Fast Interframe Transfrom Coding Based on Characteristics of Transform Coefficients and Frame Difference. 449-452 - J. A. Provine, Leonard T. Bruton:
Lip Synchronization in 3-D Model Based Coding for Video-Conferencing. 453-456 - Touradj Ebrahimi, Homer H. Chen, Barry G. Haskell:
A Region Based Motion Compensated Video Codec for Very Low Bitrate Applications. 457-461 - Dong-Il Chang, Young-Kwon Cho, Souguil Ann:
A New Wavelet Tranform-Based CELP Coder with Band Selection and Selective VQ. 462-465 - Keith Hung-Kei Chow, Ming L. Liou:
Simple Cell Admission Control and Buffer Management Scheme for Mulitclass Video-On-Demand Service. 466-469 - R. K. Bertschmann, N. R. Bartley, Leonard T. Bruton:
A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video Processing. 470-473
Neural Network Theory
- Raffaele Parisi, Elio D. Di Claudio, Gianni Orlandi:
Total Least Squares Approach for Fast Learning in Multilayer Neural Networks. 474-477 - Wu Meng, Feng Guangzeng:
A Multi-Solution Learning Algorithm for Fuzzy Rules. 478-481 - Yoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai:
A Self-Organized Network with a Supervised Training. 482-485 - Jun Wang, Ce Zhu, Chenwu Wu, Zhenya He:
Neural Network Approaches to fast and Low Rate Vector Quantization. 486-489 - Ajit Dingankar, Irwin W. Sandberg:
On Error Bounds for Neural Network Approximation. 490-492 - Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Convergence of Hopfield Neural Network for Orthogonal Transformation. 493-496 - Tzuu-Hseng S. Li, Chyi-Cherng Lai:
Lyapunov Function Based Fuzzy State Estimator. 497-500 - Mark P. Joy, Vedat Tavsanoglu:
Circulant Matrices and the Stability of Ring CNNs. 501-504 - Paolo Arena, Luigi Fortuna, Giovanni Muscato, Maria Gabriella Xibilia
Fast Learning by Weight Estimation in Complex Valued MLPs. 505-508
Combinatronics in Advanced CAS II
- Morikazu Nakamura, Kenji Onaga, Seiki Kyan, Manuel Silva:
A Genetic Algorithm for Sex-Fair Stable Marriage Problem. 509-512 - Masato Nakagawa, Dong-Ik Lee, Sadatoshi Kumagai, Shinzo Kodama:
Equivalent Net Abstraction and Firing Sequence Preservation. 513-516 - Tadao Murata, Jaegeol Yim:
Petri-Net Methods for Reasoning in Real-Time Control Systems. 517-520 - Atsushi Togashi, Nobuyuki Usui, Kukhwan Song, Norio Shiratori:
A Derivation of System Specifications Based on a Partial Logical Petri Net. 521-524
Analog-To-Digital Converters I
- João Goes, João C. Vital, José E. Franca:
Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration. 525-528 - Jorge Guilherme, José E. Franca:
New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures. 529-532 - Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno:
A Self-Calibrating A/D Converter Using T-Model Neural Network. 533-536 - Chih-Cheng Chen, Chung-Yu Wu, Jyh-Jer Cho:
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction. 537-540 - Andreas Häberli, Piero Malcovati, Henry Baltes, Franco Maloberti:
An Incremental A/C Converter for Accurate Vector Probe Measurements. 541-544
VLSI DSP I
- Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen:
A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. 545-548 - Hsiang-Ling Li, Chaitali Chakrabarti:
A New Viterbi Decoder Design for Code Rate K/N. 549-552 - Arun Raghupathy, Ut-Va Koc, K. J. Ray Liu:
A Waveront Array for URV Decomposition Updating. 553-556 - Naresh R. Shanbhag, Gi-Hong Im:
Pipelined Adaptive IIR Filter Architecture. 558-561 - Peter Pirsch, Johannes Kneip, Karsten Rönner:
Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. 562-565
Timing Simulation
- Vigyan Singhal, Robert K. Brayton, Carl Pixley:
Power-Up Delay for Retiming Digital Circuits. 566-569 - Jeong-Taek Kong, David Overhauser:
Combining RC-Interconnect Effects with Nonlinear MOS Macromodels. 570-573 - Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su:
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. 574-577 - Jeong-Taek Kong, Syed Zakir Hussain, David Overhauser:
Improving Digital MOS Macromodel Accuracy. 578-581 - Syed Zakir Hussain, David Overhauser:
Automatic Dynamic Mixed-Mode Simulation Through Network Reconfiguration. 582-584
Filter Banks and Multirate Processing I
- P. P. Vaidyanathan, Tsuhan Chen:
Structures for Time Reversed Inversion in Filter Banks. 585-588 - See-May Phoong, P. P. Vaidyanathan:
Efficient Recursive Computation of 1D and 2D-Quincunx IIR Wavelets. 589-592 - T. Engin Tuncer, Truong Q. Nguyen:
IIR M-Th Band Filters with Allpass Components. 593-596 - Sankar Basu, Han-Mook Choi:
Mermite-like Reduction Method for Design of Perfect Reconstruction Multiband Linear Phase Filter Banks. 597-600 - P. P. Vaidyanathan, See-May Phoong:
Reconstruction of Sequences from Nonuniform Samples. 601-604
Motion Compensated Block-Based Video Compression I
- Jian Feng, Hassan Mehrpour, Kwok-Tung Lo, A. E. Karbowiak:
Two-Layer MPEG Video Coding Algorithm for ATM Networks. 605-608 - Marco Winzker, Peter Pirsch, Jochen Reimers:
Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. 609-612 - Yanghoon Kim, Chong S. Rim, Byoungki Min:
A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design. 613-616 - Michael C. Chen, Alan N. Willson Jr.:
A High Accuracy Predictive Logarithmic Motion Estimation Algorithm for Video Coding. 617-620 - Stefan Honken, Feng-Ming Yang, Rainer Laur:
A HDTV-Suited Architecture for a Fast Full Search Block-Matching Algorithm. 621-624
Mathematical Treatment of Delta-Sigma Modulators
- Chris Dunn, Mark B. Sandler:
Linearising Sigma-Delta Modulators Using Dither and Chaos. 625-628 - Thomas P. Borsodi, Behrouz Nowrouzian:
Closed-Form Solution of Granular Quantization Error for a Class of Sigma-Delta Modulators. 629-632 - Montgomery Goodson, Bo Zhang, Richard Schreier:
Proving Stability of Delta-Sigma Modulator Using Invariant Sets. 633-636 - Benoît R. Veillette, Gordon W. Roberts:
Bandpass Signal Generation Using Delta-Sigma Modulation Techniques. 637-640 - Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel:
Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems. 641-644
Theory and Implementation of Cellular Neural Networks
- Johan A. K. Suykens, Joos Vandewalle:
Generalized Cellular Neural Networks Represented in he NLq Framework. 645-648 - Benzheng Xiao:
An Algebraic Construct Method for Cellular Neural Networks. 649-652 - Bing J. Sheu, Sa Hyun Bang, Wai-Chi Fang:
VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. 653-656 - Servando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez:
Realization of a CNN Universal Chip in CMOS Technolgy. 657-659 - R. Yentis Jr., C. A. Zincke, Mona E. Zaghloul, Michael Gaitan:
Micromachined Display Ouptut for a Cellular Neural Network. 660-663
Circuit Theory Approach to Mechatronics I
- Timo Veijola, Tapani Ryhänen:
Model of Capacitive Micromechanical Accelerometer Including Effect of Squeezed Gas Film. 664-667 - Johan Scholliers
A SPICE-Based Library for Mechatronic Systems. 668-671 - Jacek Wojciechowski, Leszek J. Opalski, Krzysztof Zamlynski:
From Circuit to Mechatronic System Tolerance Optimization. 672-675 - Herman Mann:
Mixed Energy-Domain Multipoles and Multiports. 676-679
Synchronization and Control of Chaotic Systems I
- Ute Feldmann, Martin Hasler, Wolfgang M. Schwarz:
Communication by Chaotic Signals: The Inverse System Approach. 680-683 - René Lozi:
Secure communications via chaotic synchronization in Chua's circuit and Bonhoeffer-Van der Pol equation: numerical analysis of the errors of the recovered signal. 684-687 - T. L. Carroll:
Using Filters for Chaotic Synchronization for Communications. 688-691 - Patrick Celka:
Synchronization of Chaotic Systems Through Parameter Adaptation. 692-695
Analog-to-Digital Converters II
- K. Nagaraj:
Self-Calibration Technique for Pipe-Lined Algorithmic ADC. 696-699 - Haruo Kobayashi, Hiroshi Sakayori, Tsutomu Tobari, Hiroyuki Matsuura:
Error Correction Algorithm for Folding/Interpolation ADC. 700-703 - Richard Mason, John T. Taylor:
High-Speed, High-Reslution Analogue-To-Digital Conversion Using a Hybrid Electro-Optic Approach. 704-707 - Donald M. Hummels, Wahid Ahmed, Fred H. Irons:
Measurement of Random Sample Time Jitter for ADCs. 708-711
VLSI DSP II
- Eddie G. Tzeng, Chen-Yi Lee:
An Efficient Memory Architecture for Motion Estimation Processor Design. 712-715 - Min-Hsiung Lin, Gee-gwo Mei, Thomas A. Horvath, Robert J. Yagley, Roger S. Rutter:
A Novel Memory Architecture to Achieve Minimal Rounding/Truncation Errors for N Dimensional Image Transformation. 716-719 - Yongjin Jeong, Wayne P. Burleson:
High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding. 720-723 - Dawood Alam, Stuart S. Lawson:
VLSI Implementation of a New Bit-Level Pipelined Architecture for 2-D Allpass Digital Filters. 724-727
Circuit Simulation
- Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Improving Parallel Circuit Simulation Using High-Level Waveforms. 728-731 - Scott vpn Tonningen, Michael D. Ciletti:
ADM: A New Technique for the Simulation of CMOS Circuit Transients. 732-735 - Mark C. Williams, Ronald S. Vogelsong, Kenneth S. Kundert:
Simulation and Modelling of Nonlinear Magnetics. 736-739 - Hiroshi Ninomiya, Hideki Asai:
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. 740-743
Filter Banks and Multirate Processing II
- Tanja Karp, Norbert J. Fliege:
MDFT Filter Banks with Perfect Reconstruction. 744-747 - Huan Yan, Masaaki Ikehara:
Modulated 2 Dimensional Perfect Reconstruction FIR Filter Banks with Permissible Passbands. 748-751 - Yuan-Pei Lin, P. P. Vaidyanathan:
Two-Dimensional Paraunitary Cosine Modulated Perfect Reconstruction Filter Banks. 752-755 - Shogo Muramatsu, Hitoshi Kiya:
Multidimensional Parallel Processing Methods for Rational Sampling Lattice Alteration. 756-759 - Kaoru Kurosawa, Naonori Yamashita:
Power Complementary and Linear Phase Filter Banks. 760-763
Motion Compensated Block-Based Video Coding II
- Hain-Ching Liu, Gregory L. Zick:
Automatic Determination of Scene Changes in MPEG Compressed Video. 764-767
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