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ISLPED 2019: Lausanne, Switzerland
- 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019. IEEE 2019, ISBN 978-1-7281-2954-9
- Ricardo Gomez Gomez, Edwige Bano, Sylvain Clerc:
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology. 1-6 - Venkata Chaitanya Krishna Chekuri
, Nihar Dasari, Arvind Singh, Saibal Mukhopadhyay:
Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs. 1-6 - Leul Belayneh, Abraham Addisie, Valeria Bertacco:
MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph Analytics. 1-6 - Da Eun Shim, Sai Pentapati, Jeehyun Lee, Yun Seop Yu, Sung Kyu Lim:
Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs. 1-6 - Sami Salamin, Martin Rapp, Hussam Amrouch
NCFET-Aware Voltage Scaling. 1-6 - Pavan Kumar Chundi, Peiye Liu, Sangsu Park, Seho Lee, Mingoo Seok:
FPGA-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory Access. 1-6 - Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger
Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers. 1-6 - Brian Crafton, Matt West, Padip Basnet, Eric Vogel, Arijit Raychowdhury:
Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment. 1-6 - Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo:
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. 1-6 - Young Geun Kim, Jeong In Kim, Seung Hun Choi, Seon Young Kim, Sung Woo Chung:
Temperature-aware Adaptive VM Allocation in Heterogeneous Data Centers. 1-6 - Taegeun Yoo, Hyunjoon Kim
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. 1-6 - Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. 1-4 - Saransh Gupta, Mohsen Imani, Behnam Khaleghi, Venkatesh Kumar, Tajana Rosing:
RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment. 1-6 - Mingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. 1-6 - Muhammad Abdullah Hanif, Muhammad Zuhaib Akbar, Rehan Ahmed, Semeen Rehman, Axel Jantsch
MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks. 1-6 - Lejie Lu, Richard Afoakwa, Michael C. Huang
Concurrent Multipoint-to-Multipoint Communication on Interposer Channels. 1-6 - Donkyu Baek, Yukai Chen
Battery-Aware Electric Truck Delivery Route Planner. 1-6 - Halil Andaç Yigit, Hasan Ulusan
A Pulse-Width Modulated Cochlear Implant Interface Electronics with 513 µW Power Consumption. 1-5 - Dong Kai Wang
A2M: Approximate Algebraic Memory Using Polynomials Rings. 1-6 - Hyeonwook Wi, Hyeonuk Kim
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration. 1-6 - Junseo Jo, Jaeha Kung
Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition. 1-6 - Benjamin J. Fletcher
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. 1-6 - Aporva Amarnath, Javad Bagherzadeh, Jielun Tan, Ronald G. Dreslinski:
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology. 1-6 - Hao-Chun Chang, Yu-Chieh Yang, Liang-Yan Yu, Chun-Han Lin
FLASH: Content-based Power-saving Design for Scrolling Operations in Browser Applications on Mobile OLED Devices. 1-6 - Yong-Un Jeong, Joo-Hyung Chae
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. 1-6 - Halima Najibi, Alexandre Levisse, Marina Zapater:
A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays. 1-6 - Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks. 1-6 - Yu-Pei Liang, Tseng-Yi Chen
Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. 1-6 - Jaehyun Kim, Chaeun Lee, Jihun Kim, Yumin Kim, Cheol Seong Hwang, Kiyoung Choi:
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks. 1-6 - Mahabubul Alam, Abdullah Ash-Saki
Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits. 1-6 - Justin Morris
CompHD: Efficient Hyperdimensional Computing Using Model Compression. 1-6 - Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs. 1-6 - Yu-Chen Lin, Pi-Cheng Hsiu
Autonomous I/O for Intermittent IoT Systems. 1-6 - Kyuseung Han
TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. 1-6 - Xiao Liu, Mingxuan Zhou, Tajana Simunic Rosing, Jishen Zhao:
HR3AM: A Heat Resilient Design for RRAM-based Neuromorphic Computing. 1-6 - Lile Cai, Anne-Maelle Barneche, Arthur Herbout, Chuan Sheng Foo, Jie Lin, Vijay Ramaseshan Chandrasekhar, Mohamed M. Sabry Aly:
TEA-DNN: the Quest for Time-Energy-Accuracy Co-optimized Deep Neural Networks. 1-6 - Di Zhu, Yunfan Li, Lizhong Chen:
On Trade-off Between Static and Dynamic Power Consumption in NoC Power Gating. 1-6 - Jiheon Park, Young-Ha Hwang
A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode. 1-6 - Heetak Kim, Hoyoung Tang, Jongsun Park
An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. 1-6 - Youngtae Yang, Jun Soo Cho, Byunggyu Lee, Suhwan Kim:
A Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface for Speech Recognition. 1-6 - Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, Yanzhi Wang:
An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM. 1-6 - Cong Thuan Do, Young-Ho Gong, Cheol Hong Kim, Seon Wook Kim, Sung Woo Chung:
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. 1-6 - Sandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation. 1-6 - Michael Stokes, Ryan Baird, Zhaoxiang Jin, David B. Whalley, Soner Önder:
Improving Energy Efficiency by Memoizing Data Access Information. 1-6 - Joonas Multanen, Pekka Jääskeläinen
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. 1-6 - Amir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram:
BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services. 1-6 - Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis:
Robust Low Power Clock Synchronization for Multi-Die Systems. 1-6 - Di Wu, Tianen Chen, Chien-Fu Chen
SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization. 1-6 - Zihao Yuan
Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers. 1-6 - Supreet Jeloka, Pranay Prabhat
A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy. 1-6 - Sayandip De, Jos Huisken
An Automated Approximation Methodology for Arithmetic Circuits. 1-6 - Sangwoo Jung
WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator. 1-6 - Karthikeyan Nagarajan, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh, Anupam Chattopadhyay:
SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing. 1-6 - Daniele Jahier Pagliari
CNN-Based Camera-less User Attention Detection for Smartphone Power Management. 1-6 - Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline:
Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. 1-6 - Federico Reghenzani
A Probabilistic Approach to Energy-Constrained Mixed-Criticality Systems. 1-6 - Tianhao Shen, Di Gao, Yiyu Shi, Cheng Zhuo:
Power Delivery Resonant Virus: Concept and Applications. 1-6
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