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ISPASS 2021: Stony Brook, NY, USA
- IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021. IEEE 2021, ISBN 978-1-7281-8643-6
Paper Session I: Benchmarking
- Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy
, Reetuparna Das
GenomicsBench: A Benchmark Suite for Genomics. 1-12 - Trinayan Baruah, Kaustubh Shivdikar
GNNMark: A Benchmark Suite to Characterize Graph Neural Network Training on GPUs. 13-23 - Fei Tang, Wanling Gao, Jianfeng Zhan, Chuanxin Lan, Xu Wen, Lei Wang, Chunjie Luo, Zheng Cao
AIBench Training: Balanced Industry-Standard AI Training Benchmarking. 24-35
Paper Session II: GPUs
- Petros Anastasiadis
CoCoPeLia: Communication-Computation Overlap Prediction for Efficient Linear Algebra on GPUs. 36-47 - Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. 48-58 - Shougang Yuan, Ardhi Wiratama Baskara Yudha, Yan Solihin, Huiyang Zhou
Analyzing Secure Memory Architecture for GPUs. 59-69
Poster Session A
- Gokul Subramanian Ravi, Ramon Bertran, Pradip Bose, Mikko H. Lipasti:
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing. 70-72 - Navneet Raju, Rahul M. Koushik, Hari Om, Subramaniam Kalambur:
ViStA: Video Streaming and Analytics Benchmark. 73-75 - Suyash Bakshi, S. Lennart Johnsson:
Analysis of Factors Affecting Power Consumption and Energy Efficiency of SGEMM on the Low-Power Myriad-2 VPU. 76-78 - Pete Ehrett, Nathan Block, Bing Schaefer, Adrian Berding, John Paul Koenig, Pranav Srinivasan, Valeria Bertacco, Todd M. Austin:
A Defense-Inspired Benchmark Suite. 79-80 - Sri Harsha Gade, Anup Gangwar, Ambica Prasad, Nitin Kumar Agarwal, Ravishankar Sreedharan:
An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases. 81-83 - Mohsen Koohi Esfahani
How Do Graph Relabeling Algorithms Improve Memory Locality? 84-86 - Emir C. Marangoz, Kyoung-Don Kang, Seunghee Shin:
Designing GPU Architecture for Memory Bandwidth Reservation. 87-89 - Wei Zhang, Wei Wei, Wen Wang, Lingling Jin, Zheng Cao
Reducing BERT Computation by Padding Removal and Curriculum Learning. 90-92 - Qi Pei, Seunghee Shin:
Efficient Split Counter Mode Encryption for NVM. 93-95
Paper Session III: Characterization
- Michael Buch, Zahra Azad, Ajay Joshi, Vijay Janapa Reddi:
AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones. 96-106 - Aniket Anand Deshmukh, Ruihao Li
Performance Characterization of .NET Benchmarks. 107-117 - Junwei Wu, Jingwei Sun, Hao Sun, Guangzhong Sun:
Performance Analysis of Graph Neural Network Frameworks. 118-127
Paper Session IV: Software Analysis
- Ali Mustafa Zaidi, Konstantinos Iordanou
Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach. 128-138 - Bryan Harris, Michael Marzullo, Nihat Altiparmak
Real-Time Characterization of Data Access Correlations. 139-150 - Tarek Ramadan, Tanzima Z. Islam
Comparative Code Structure Analysis using Deep Learning for Performance Prediction. 151-161
Paper Session V: Best Paper Nominations
- Michael Lui, Yavuz Yetim, Özgür Özkan, Zhuoran Zhao, Shin-Yeh Tsai, Carole-Jean Wu, Mark Hempstead
Understanding Capacity-Driven Scale-Out Neural Recommendation Inference. 162-171 - Yasuo Ishii, Jaekyu Lee, Krishnendra Nathella, Dam Sunwoo:
Re-establishing Fetch-Directed Instruction Prefetching: An Industry Perspective. 172-182 - Bobby R. Bruce
Enabling Reproducible and Agile Full-System Simulation. 183-193 - Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power
A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems. 194-204 - Mengchi Zhang
Characterizing Massively Parallel Polymorphism. 205-216
Poster Session B
- Jiansong Li
Pinpointing the Memory Behaviors of DNN Training. 217-219 - Guru Prasad Srinivasa, David Werner, Mark Hempstead
Thermal-Aware Overclocking for Smartphones. 220-222 - Pablo Bodmann, George Papadimitriou, Dimitris Gizopoulos, Paolo Rech:
The Impact of SoC Integration and OS Deployment on the Reliability of Arm Processors. 223-225 - Jingyi Xu, Sehoon Kim, Borivoje Nikolic
Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms. 226-228 - Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze:
Architecture-Level Energy Estimation for Heterogeneous Computing Systems. 229-231 - Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer:
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. 232-234 - Eduardo José Gómez-Hernández
Splash-4: Improving Scalability with Lock-Free Constructs. 235-236 - Wonkyung Jung, Eojin Lee, Sangpyo Kim, Namhoon Kim, Keewoo Lee, Chohong Min, Jung Hee Cheon, Jung Ho Ahn
Accelerating Fully Homomorphic Encryption Through Microarchitecture-Aware Analysis and Optimization. 237-239 - Subhankar Pal
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. 240-242
Paper Session VI: Datacenters and HPC
- Zahra Azad, Rathijit Sen, Kwanghyun Park
Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads? 243-253 - Abenezer Wudenhe, Hung-Wei Tseng
TPUPoint: Automatic Characterization of Hardware-Accelerated Machine-Learning Behavior for Cloud Computing. 254-264 - Takuya Fukuoka, Shigeyuki Sato, Kenjiro Taura
Pitfalls of InfiniBand with On-Demand Paging. 265-275 - Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang:
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. 276-287
Paper Session VII: HW and Co-Design
- Sheng-Chun Kao, Tushar Krishna:
E3: A HW/SW Co-design Neuroevolution Platform for Autonomous Learning in Edge Device. 288-298 - Nathan Pemberton, Alon Amid:
FireMarshal: Making HW/SW Co-Design Reproducible and Reliable. 299-309 - Jerry Zhao, Abraham Gonzalez, Alon Amid, Sagar Karandikar, Krste Asanovic:
COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors. 310-320
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