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20th SMACD 2024: Volos, Greece
- 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024, Volos, Greece, July 2-5, 2024. IEEE 2024, ISBN 979-8-3503-5192-7
- Ahmed Hossam-Eldeen, Bowen Wang, Priyanka Pandey, Marie Garcia Bardon, Fernando García-Redondo:
DTCO for Fast STT-MRAM Periphery Operation. 1-4 - Pierre Graindorge, Bowen Wang, Marie Garcia Bardon, Fernando García-Redondo:
Automatic Regression Framework for MRAM Compact Models Calibration including Stochasticity. 1-4 - Jesko Flemming, Timon Rogge, Bernhard Wicht, Pascal Witte:
A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs. 1-4 - Himavanth Reddy Pallapu, Gnaneswar Villuri, Alex Doboli, Simona Doboli:
Automatically Understanding Human Behavior for IoT Applications with Optimized Human-in-the-Loop Control. 1-4 - Benjamin Prautsch, Ralf Sommer, Jürgen Scheible, Uwe Eichler, Lorenz Renner, Till Moldenhauer, Matthias Schweikardt, Yannick Uhlmann:
Integrating Multiple Knowledge-based Automation Methodologies into the A/MS IC Design Flow. 1-4 - F. J. Rubio-Barbero, F. de Los Santos-Prieto, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Harvesting RTN for True Random Number Generators and Physical Unclonable Functions. 1-4 - Susann Rothe, Jens Lienig, Sachin S. Sapatnekar:
Stress-based Electromigration Modeling in IC Design: Moving from Theory to Practice. 1-4 - Andreas Tsiougkos, Moschos Antoniadis, Vasilis F. Pavlidis:
Two Stage Diode-String Architecture for Ultra-Low Power Digital to Analog Converters. 1-4 - Alberto Musa, Emanuele Parisi, Luca Barbierato, Andrea Acquaviva, Francesco Barchi:
End-to-end Integration of OpenTitan Security Features in a Pure RISC-V SoC. 1-4 - Sergio Palomeque-Mangut, Pablo Fernández-Peramo, Juan A. Leñero-Bardallo, Ángle Rodríguez-Vázquez:
Analysis and Simulation of Reset Leakage Currents and Quantization Error in a PFM Digital Pixel. 1-4 - Franco Volante, Francesco Barchi, Edoardo Patti, Lorenzo Bottaccioli, Luca Barbierato:
OP-TEE powered OpenSSL Engine enhancing Digital Signature security for ARM Architectures. 1-4 - Pedro Eid, Filipe Azevedo, Ricardo Martins, Nuno Lourenço:
Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models. 1-4 - Arne von Zedlitz-Neukirch, David Bierbuesse, Renato Negra:
Bidirectional CAN-Interface Using Inductive Transmission. 1-4 - Michele Caselli, Andrea Boni:
An Optimization Framework for Mixed-Signal Accelerators Based on F-2T2R Compute Cells. 1-4 - Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Abel Naya, Santiago Celma:
Proposal and Implementation on Smartphone of a PUF Using Accelerometers and Gyroscopes. 1-4 - Vishnu Pathak, Karthik Salian, Husni Habal, Marco De Maina:
Analog Circuit Classification Using Graph Convolution Networks. 1-4 - Jonghyeon Nam, Jaeduk Han, Hokeun Kim:
Low-Power Encoding for PAM-3 DRAM Bus. 1-4 - Francisco Aznar, Uxua Esteban-Eraso, Antonio D. Martínez-Pérez, Santiago Celma:
A New Metric Measuring Steering Accuracy of Digitally Controlled Phase Shifters. 1-4 - Michel Chevalier, Severin Trochut, Roberto Guizzetti, Pascal Urard, Lioua Labrak, John Samuel, Remy Cellier, Nacer Abouchi:
Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms. 1-4 - Davide Basso, Luca Bortolussi, Mirjana S. Videnovic-Misic, Husni Habal:
Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees. 1-4 - Enes Saglican, Engin Afacan:
An Open-Source ANN-based Analog/RF Intellectual Property for SkyWater130nm Technology. 1-4 - Fábio Passos, Ricardo M. F. Martins, Nuno Lourenço:
Low-Power 9.6-11GHz and 10.8-12GHz VCOs Designed for a 2.5/5GHz TRx using High-Q Inductors Synthesized with ML Techniques. 1-4 - Giulia Di Capua, Nicola Femia, Nunzio Oliva, Luca De Guglielmo:
Method, Test Procedure and System for the Experimental Characterization of Power Inductors. 1-4 - Fanny Spagnolo, Pasquale Corsonello:
Carry-chain based Ring Oscillator Design for Temperature Sensing on FPGAs. 1-4 - Martin Grabmann, Eric Schäfer, Georg Gläser:
Propagation Delay Estimation for Mixed-Signal Modeling of Comparators. 1-4 - Jonas Mair, Sabitha Kusuma, Dennis Liebau, Lammert Duipmans, Lea Schreckenberg, Patrick Vliex, André Zambanini, Stefan van Waasen:
Rapid Prototyping Platform for Integrated Circuits for Quantum Computing. 1-4 - Nellie Laleni, Thomas Kämpfe:
An Efficient FeFET-Based Compute-In-Memory Macro Readout Inspired by the 3T Pixel Array Cell. 1-4 - Rafael Vieira, Seyedehsomayeh Hatefinasab, Ricardo Martins, Nuno Horta, Nuno Lourenço:
A 25 nW Heartbeat Monitoring Circuit for Wearable Applications in CMOS 65nm. 1-4 - Corrado De Sio, Giorgio Cora, Sarah Azimi, Eleonora Vacca, Luca Sterpone:
Exploring the Resiliency of Hardware CNN for Aerospace Application. 1-4 - Catalin Visan, Dan Curavale, Georgian Nicolae, Mihai Boldeanu, Horia Cucu, Andi Buzo:
A novel simulations scheduler for automated circuit sizing algorithms. 1-4 - Patricio Carrasco, Ioannis Vourkas:
FPGA Implementation of an Elementary ReRAM Memory Control Unit. 1-4 - Yijia Hao, Miguel Gandara, Srinjoy Mitra, Sandy Cochran, Bo Liu:
Design of a Two-Stage Miller-Compensated Operational Amplifier Using an EDA Tool-Centered Approach. 1-4 - Giulia Di Capua, Antonio Maffucci, Nicola Femia, Andrea Gaetano Chiariello:
Analysis of Capacitive Coupling and Crosstalk in the PCB of Switch-Mode Power Supplies. 1-4 - Andrea Boni, Michele Caselli:
A CAD Toolbox for the Automatic Design and Optimization of ULP CMOS Voltage References. 1-4 - Alexandra Takou, Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis:
Sensitivity-aware Hardware Trojan Injection for SET Propagation and Soft Error Attacks. 1-4 - Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon:
Efficient Stimuli Generation using Reinforcement Learning in Design Verification. 1-4 - R. Alp Akpinar, Sreekar Achanta, Abbas Fotouhi, Hanwen Zhang, Daniel J. Auger:
Battery Temperature Prediction in Electric Vehicles Using Bayesian Regularization. 1-4 - Veeti Lahtinen, Santeri Porrasmaa, Marko Kosunen, Jussi Ryynänen:
Procedural Design, Verification and Implementation Framework for Analog Amplifiers. 1-4 - Anastasios Michailidis, Thomas Noulis:
Algorithm-based Wide-Band Impedance Matching Network Synthesis and Optimization. 1-4 - Chrysostomos Chatzigeorgiou, George Floros, Dimitrios Chatzigeorgiou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
Efficient Parametric Model Order Reduction for Large-Scale Circuit Models using Extended Krylov Subspace. 1-4 - Pavlos Stoikos, George Floros, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis:
A Fast Security Closure Approach for EM-based Attacks on General Multi-Segment Interconnects. 1-4 - Markus Leibl, Helmut Graeb:
Optimizer-Free Sizing of OpAmps Leveraging Structural and Functional Properties. 1-4 - Diogo Peneda, Filipe Azevedo, Nuno Lourenço, Nuno Horta, Ricardo Martins:
Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation. 1-4 - Nico Corsinovi, Emanuele Pagani, Roberto Ciardi, Matteo Bertolucci, Luca Fanucci:
Design and Development of a Linear Adaptive Equalizer used for High Data-Rate Satellite Receivers based on CCSDS 131.2-B Standard. 1-4 - Michele Caselli, Andrea Boni, Stefano Caselli:
A PWM-SAR ADC with Asynchronous Control Unit for Mixed-Signal Accelerators. 1-4 - Yasmine Abu-Haeyeh, Lars Hedrich:
Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction. 1-4 - Jiaxiang Pan, Zhufei Chu:
Area-Aware Logic Mapping for MAGIC based In-Memory Computing. 1-4 - Antonios Keremidis, Stylianos Tzelepis, Alkis Hatzopoulos:
The Integration and Testing Procedures for the AcubeSAT Nanosatellite's Software. 1-4 - Jonas Lienke, Florian Kögler, Eric Schäfer, Georg Gläser:
Set the Clock: A Synthesizable Clock Manager. 1-4 - Pablo Fernández-Peramo, Juan A. Leñero-Bardallo, Sergio Palomeque-Mangut, Ángel Rodríguez-Vázquez:
A Verilog-A/MS Compact Model for the Temperature Dependency of the Open-Circuit Voltage for Integrated Diodes. 1-4 - M. Shamookh, Arun Ashok, Andre Zambanini, Anton Geläschus, Christian Grewing, Andreas Bahr, Stefan van Waasen:
3.35V High Voltage Electroforming Generator in 28nm with 5.3mV ripple and 46% efficiency for HfO2-based Memristors. 1-4 - Anastasis Vagenas, Dimitrios Garyfallou, Nestoras E. Evmorfopoulos, George I. Stamoulis:
A learning-based method for performance optimization of timing analysis. 1-4 - Haik Manukian, Osama Nayfeh, Matthew Kelly:
Circuit Component Tolerance of Self-Organizing Logic Gates. 1-4 - Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Santiago Celma:
Towards the Implementation of a Strong PUF using Generalized Galois Ring Oscillators. 1-4 - Eleni Tselepi, Olympia Axelou, George Floros, George I. Stamoulis:
An Efficient Approach for Combined Electromigration and Thermomigration Analysis Based on the Extended Krylov Subspace. 1-4 - Hakan Taskiran, Enes Saglican, Engin Afacan:
ANN-based Analog/RF IC Synthesis Featuring Reinforcement Learning-based Fine-Tuning. 1-4 - Ricardo Martins, António Gusmão, Rafael Vieira, Fábio Passos, Nuno Lourenço, Nuno Horta:
Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline. 1-4 - Mohammad Beyki, Justus Pawlak, Robert Patzke, Franz Renz:
Photo Diode Amplifier Design for Applications in MIMOS II for Space Exploration. 1-4 - Elif Seher Serinken, Alperen Tunç, Revna Acar Vural, Mustafa Berke Yelten:
Neural Network-Based Coefficient Estimators for Memory Polynomial Digital Predistortion. 1-4 - Christos Giamouzis, Dimitrios Garyfallou, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos:
Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection. 1-4 - Ingrid Kovacs, Bianca Carbunescu-Stoenescu, Marina Dana Topa, Andi Buzo, Emilian David, Georg Pelz:
Frontend-Backend Integrated Circuit Device Linking Using Machine Learning Algorithms. 1-4 - F. de Los Santos-Prieto, F. J. Rubio-Barbero, Rafael Castro-López, E. Roca, F. V. Fernandez:
Optimization-based bit selection technique to improve the reliability of PUFs. 1-4 - Vasile Grosu, Emilian David, Liviu Goras, Georg Pelz:
Multiple Output Modelling of Integrated Circuits Behavior Using an Active Learning Approach. 1-4 - Jose M. Gata-Romero, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Towards a Digital Twin of a Time-Dependent Variability Characterization Laboratory. 1-4 - Shih-Han Chang, Shih-Yu Chen, Chun-Wen Yang, Hau-Wei Huang, Yu-Cheng Yang, Wei-Liang Chen, Chien-Nan Liu, Hung-Ming Chen:
Mitigating Power and Process Variation for Analog CIM Design Migration. 1-4 - Christos Pavlidis, Nikos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis:
Ternary Clock Tree Synthesis for 3D ICs. 1-4 - Andrés Santana-Andreo, Jose M. Gata-Romero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Streamlined design methodology for Cell-Based DCOs. 1-4 - Dimitrios A. Prousalis, Ioannis Messaris, A. A. Sayed, Vasileios G. Ntinas, Ahmet Samil Demirkol, Alon Ascoli, Ronald Tetzlaff:
Image Processing with Memristor Cellular Nonlinear Networks Featuring Volatile Threshold Switches. 1-4
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