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Amit Narayan
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2010 – 2019
- 2014
- [j2]Kyle Anderson, Jimmy Du, Amit Narayan, Abbas El Gamal:
GridSpice: A Distributed Simulation Platform for the Smart Grid. IEEE Trans. Ind. Informatics 10(4): 2354-2363 (2014)
2000 – 2009
- 2006
- [j1]J. Ramanujam
, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan, Ankush Agarwal:
Estimating and reducing the memory requirements of signal processing codes for embedded systems. IEEE Trans. Signal Process. 54(1): 286-294 (2006) - 2005
- [c17]Amit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan:
Steady-state analysis of voltage and current controlled oscillators. ICCAD 2005: 618-623 - 2004
- [c16]Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson:
A Partitioning Methodology for BDD-Based Verification. FMCAD 2004: 399-413 - [c15]Makram M. Mansour, Amit Mehrotra, William W. Walker, Amit Narayan:
Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. ISCAS (5) 2004: 512-515 - [c14]Suihua Lu, Amit Narayan, Amit Mehrotra:
Continuation method in multitone harmonic balance. ISCAS (5) 2004: 520-523 - 2003
- [c13]Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain:
Improved Symbolic Verification Using Partitioning Techniques. CHARME 2003: 410-424 - 2001
- [c12]J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan:
Reducing Memory Requirements of Nested Loops for Embedded Systems. DAC 2001: 359-364
1990 – 1999
- 1998
- [c11]Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Wireplanning in logic synthesis. ICCAD 1998: 26-33 - 1997
- [c10]Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Reachability analysis using partitioned-ROBDDs. ICCAD 1997: 388-393 - [c9]Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Logic synthesis for large pass transistor circuits. ICCAD 1997: 663-670 - [c8]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD 1997: 445-454 - [c7]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Combinational Circuit. VLSI Design 1997: 218-225 - 1996
- [c6]Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456 - [c5]Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434 - [c4]Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD 1996: 547-554 - [c3]Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253 - 1995
- [c2]J. Ramanujam, Amit Narayan:
Integrating Data Distribution and Loop Transformations. PP 1995: 668-673 - 1994
- [c1]Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli:
Measurement and modeling of MOS transistor current mismatch in analog IC's. ICCAD 1994: 272-277
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