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Tuo Li 0001
Person information
- affiliation: Institute of Computing Technology, CAS, China
- affiliation (former): University of New South Wales, Australia
Other persons with the same name
- Tuo Li — disambiguation page
- Tuo Li 0002 — Renmin University of China, Beijing, P.R. China
- Tuo Li 0003 — Hexi University
- Tuo Li 0004 — Miami University, Department of Electrical and Computer Engineering, Oxford, OH, USA
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2020 – today
- 2024
- [j5]Sajid Hussain
, Hui Guo
MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. 21(4): 3719-3733 (2024) - [c14]Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran
Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. DATE 2024: 1-6 - 2022
- [c13]Tuo Li, Sri Parameswaran
FaSe: fast selective flushing to mitigate contention-based cache timing attacks. DAC 2022: 541-546 - [c12]Hsu-Kang Dow, Tuo Li, Sri Parameswaran
HWST128: complete memory safety accelerator on RISC-V with metadata compression. DAC 2022: 709-714 - [i2]Tuo Li, Sri Parameswaran
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. CoRR abs/2204.05508 (2022) - 2021
- [j4]Sajid Hussain
COPS: A complete oblivious processing system. Microprocess. Microsystems 85: 104295 (2021) - [c11]Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. DAC 2021: 289-294 - 2020
- [j3]Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
Hardware Trojan Mitigation in Pipelined MPSoCs. ACM Trans. Design Autom. Electr. Syst. 25(1): 6:1-6:27 (2020) - [c10]Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. VLSID 2020: 84-89 - [i1]Tuo Li, Bradley Hopkins, Sri Parameswaran:
SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. CoRR abs/2011.10249 (2020)
2010 – 2019
- 2017
- [j2]Tuo Li, Muhammad Shafique
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers 66(4): 647-660 (2017) - 2016
- [j1]Tuo Li
Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. 49(3): 57:1-57:44 (2016) - [c9]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
RECORD: Reducing register traffic for checkpointing in embedded processors. DATE 2016: 582-587 - 2015
- [c8]Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. ISCAS 2015: 413-416 - [c7]Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran
Side channel attacks in embedded systems: A tale of hostilities and deterrence. ISQED 2015: 452-459 - [c6]Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. VLSID 2015: 29-34 - 2013
- [b1]Tuo Li:
Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. University of New South Wales, Sydney, Australia, 2013 - [c5]Tuo Li, Muhammad Shafique
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. DAC 2013: 62:1-62:7 - [c4]Tuo Li, Muhammad Shafique
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE 2013: 707-712 - [c3]Tuo Li, Muhammad Shafique
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. ICCAD 2013: 646-653 - 2012
- [c2]Tuo Li, Roshan G. Ragel, Sri Parameswaran
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. DATE 2012: 875-880 - [c1]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
Fine-grained hardware/software methodology for process migration in MPSoCs. ICCAD 2012: 508-515
Coauthor Index
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