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Christopher J. Hughes
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2020 – today
- 2024
- [c34]Dongho Ha, Yunan Zhang, Chen-Chien Kao, Christopher J. Hughes, Won Woo Ro, Hung-Wei Tseng:
M3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. SC 2024: 10 - 2023
- [c33]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya
, Eric Qin, Christopher J. Hughes
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. HPCA 2023: 259-272 - [i4]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. CoRR abs/2302.08687 (2023) - 2022
- [c32]Zhangxiaowen Gong, Houxiang Ji
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. ISCA 2022: 916-931 - 2021
- [c31]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. DAC 2021: 253-258 - [c30]Rohan Baskar Prabhakar, Sachit Kuhar, Rohit Agrawal, Christopher J. Hughes
SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference. ICS 2021: 279-290 - [i3]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. CoRR abs/2110.01752 (2021) - 2020
- [c29]Zhangxiaowen Gong, Houxiang Ji
SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. PACT 2020: 279-292 - [c28]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9 - [c27]Zhangxiaowen Gong, Houxiang Ji
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. MICRO 2020: 796-810
2010 – 2019
- 2019
- [c26]Sunjae Park, Christopher J. Hughes
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory. PACT 2019: 192-204 - [c25]Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM 2019: 181-189 - [i2]Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas:
SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. CoRR abs/1911.10175 (2019) - 2018
- [c24]Sunjae Park, Christopher J. Hughes
Transactional pre-abort handlers in hardware transactional memory. PACT 2018: 33:1-33:11 - [c23]Berkin Akin, Chiachen Chou, Jongsoo Park, Christopher J. Hughes
Dynamic fine-grained sparse memory accesses. MEMSYS 2018: 85-97 - 2017
- [c22]Xiangyao Yu, Christopher J. Hughes
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation. MICRO 2017: 1-14 - [i1]Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas:
Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation. CoRR abs/1704.02677 (2017) - 2016
- [c21]Sunjae Park, Milos Prvulovic, Christopher J. Hughes
PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory. HPCA 2016: 285-296 - 2015
- [b2]Christopher J. Hughes
Single-Instruction Multiple-Data Execution. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00618-0 - [c20]Xiangyao Yu, Christopher J. Hughes
IMP: indirect memory prefetcher. MICRO 2015: 178-190 - 2013
- [c19]Simon J. Pennycook
Exploring SIMD for Molecular Dynamics, Using Intel® Xeon® Processors and Intel® Xeon Phi Coprocessors. IPDPS 2013: 1085-1097 - [c18]Richard M. Yoo, Christopher J. Hughes
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. SC 2013: 19:1-19:11 - [c17]Jongsoo Park, Richard M. Yoo, Daya Shanker Khudia, Christopher J. Hughes
Location-aware cache management for many-core processors with deep cache hierarchy. SC 2013: 20:1-20:12 - [c16]Richard M. Yoo, Christopher J. Hughes
Locality-aware task management for unstructured parallelism: a quantitative limit study. SPAA 2013: 315-325 - 2011
- [j6]Guru Venkataramani, Christopher J. Hughes
DeFT: Design space exploration for on-the-fly detection of coherence misses. ACM Trans. Archit. Code Optim. 8(2): 8:1-8:27 (2011) - [c15]Jungju Oh, Christopher J. Hughes
LIME: a framework for debugging load imbalance in multi-threaded execution. ICSE 2011: 201-210 - [c14]Guangyu Sun, Christopher J. Hughes
Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA 2011: 377-388 - 2010
- [j5]Christopher J. Hughes
Performance and Energy Implications of Many-Core Caches for Throughput Computing. IEEE Micro 30(6): 25-35 (2010)
2000 – 2009
- 2009
- [j4]Kisun You, Jike Chong, Youngmin Yi, Ekaterina Gonina, Christopher J. Hughes
Parallel scalability in speech recognition. IEEE Signal Process. Mag. 26(6): 124-135 (2009) - [c13]Jike Chong, Kisun You, Youngmin Yi, Ekaterina Gonina, Christopher J. Hughes
Scalable HMM based inference engine in large vocabulary continuous speech recognition. ICME 2009: 1797-1800 - 2008
- [j3]Yen-Kuang Chen
Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications. Proc. IEEE 96(5): 790-807 (2008) - [c12]Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen
Atomic Vector Operations on Chip Multiprocessors. ISCA 2008: 441-452 - 2007
- [c11]Trista Pei-Chun Chen, Dmitry Budnikov, Christopher J. Hughes
Computer Vision on Multi-Core Processors: Articulated Body Tracking. ICME 2007: 1862-1865 - [c10]Sanjeev Kumar, Christopher J. Hughes
Carbon: architectural support for fine-grained parallelism on chip multiprocessors. ISCA 2007: 162-173 - [c9]Christopher J. Hughes
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. ISCA 2007: 220-231 - 2006
- [c8]Gang Wu, Edward Y. Chang, Yen-Kuang Chen, Christopher J. Hughes
Incremental approximate matrix factorization for speeding up support vector machines. KDD 2006: 760-766 - [c7]Sanjeev Kumar, Michael Chu, Christopher J. Hughes
Hybrid transactional memory. PPoPP 2006: 209-220 - 2005
- [j2]Christopher J. Hughes
Memory-side prefetching for linked data structures for processor-in-memory systems. J. Parallel Distributed Comput. 65(4): 448-463 (2005) - 2004
- [c6]Christopher J. Hughes
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. ISCA 2004: 138-149 - 2003
- [b1]Christopher J. Hughes:
General -Purpose Processors for Multimedia Applications: Predictability and Energy Efficiency. University of Illinois Urbana-Champaign, USA, 2003 - 2002
- [j1]Christopher J. Hughes
RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. Computer 35(2): 40-49 (2002) - [c5]Ruchira Sasanka, Christopher J. Hughes
Joint local and global hardware adaptations for energy. ASPLOS 2002: 144-155 - [c4]Rohit Jain, Christopher J. Hughes
Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. RTSS 2002: 134-145 - 2001
- [c3]Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes
Speculative precomputation: long-range prefetching of delinquent loads. ISCA 2001: 14-25 - [c2]Christopher J. Hughes
Variability in the execution of multimedia applications and implications for architecture. ISCA 2001: 254-265 - [c1]Christopher J. Hughes
Saving energy with architectural and frequency adaptations for multimedia applications. MICRO 2001: 250-261
Coauthor Index
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