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Pavel Kubalík
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2020 – today
- 2024
- [c25]Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle:
Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA. MECO 2024: 1-4 - 2023
- [c24]Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle:
Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA. MECO 2023: 1-4 - 2022
- [c23]Miroslav Skrbek, Pavel Kubalík:
Feasibility of a Neural Network with Linearly Approximated Functions on Zynq FPGA. ICECS 2022 2022: 1-4 - [c22]Miroslav Skrbek, Pavel Kubalík:
Approximate arithmetic for modern neural networks and FPGAs. MECO 2022: 1-4 - 2020
- [j3]Matej Bartík, Tomás Benes, Pavel Kubalík:
An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs. IEEE Access 8: 183101-183116 (2020) - [c21]Vojtech Procházka, Pavel Kubalík, Hana Kubátová:
Low Power Wireless Data Transfer for Internet of Things: GSM Network Measuring Results. MECO 2020: 1-5
2010 – 2019
- 2019
- [c20]Matej Bartik, Tomás Benes, Pavel Kubalík:
Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms. CCWC 2019: 732-738 - [c19]Karel Hynek, Tomás Benes, Matej Bartik, Pavel Kubalík:
Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks. CCWC 2019: 847-851 - [c18]Tomás Benes, Matej Bartík, Pavel Kubalík:
High Throughput and Low Latency LZ4 Compressor on FPGA. ReConFig 2019: 1-5 - 2018
- [c17]Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes:
Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only). FPGA 2018: 290 - 2017
- [j2]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Design of a Residue Number System Based Linear System Solver in Hardware. J. Signal Process. Syst. 87(3): 343-356 (2017) - 2016
- [c16]Matej Bartik, Sven Ubik, Pavel Kubalík:
A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. ReConFig 2016: 1-6 - 2015
- [c15]Matej Bartik, Sven Ubik, Pavel Kubalík:
LZ4 compression algorithm on FPGA. ICECS 2015: 179-182 - 2014
- [c14]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
An ASIC linear congruence solver synthesized with three cell libraries. ICECS 2014: 706-709 - [c13]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
System on chip design of a linear system solver. ISSoC 2014: 1-6 - 2013
- [c12]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. DSD 2013: 284-287 - 2012
- [c11]Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Dedicated hardware implementation of a linear congruence solver in FPGA. ICECS 2012: 689-692 - 2011
- [c10]Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová:
Fault Models Usability Study for On-line Tested FPGA. DSD 2011: 287-290 - 2010
- [c9]Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík:
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. DSD 2010: 380-386
2000 – 2009
- 2009
- [c8]Jaroslav Borecký, Pavel Kubalík, Hana Kubátová:
Reliable Railway Station System Based on Regular Structure Implemented in FPGA. DSD 2009: 348-354 - 2008
- [j1]Pavel Kubalík, Hana Kubátová:
Dependable design technique for system-on-chip. J. Syst. Archit. 54(3-4): 452-464 (2008) - [c7]Petr Fiser, Pavel Kubalík, Hana Kubátová:
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. DSD 2008: 96-99 - [c6]Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová:
Experimental SEU Impact on Digital Design Implemented in FPGAs. DSD 2008: 100-103 - 2007
- [c5]Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová:
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. DDECS 2007: 357-360 - 2006
- [c4]Pavel Kubalík, Radek Dobias, Hana Kubátová:
Dependability Computation for Fault Tolerant Reconfigurable Duplex System. DDECS 2006: 100-102 - [c3]Pavel Kubalík, Radek Dobias, Hana Kubátová:
Dependable Design for FPGA Based on Duplex System and Reconfiguration. DSD 2006: 139-145 - [c2]Pavel Kubalík, Petr Fiser, Hana Kubátová:
Fault Tolerant System Design Method Based on Self-Checking Circuits. IOLTS 2006: 185-186 - [e1]Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2 [contents] - 2005
- [c1]Radek Dobias, Pavel Kubalík, Hana Kubátová:
Dependability computations for fault-tolerant system based on FPGA. ICECS 2005: 1-4
Coauthor Index
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