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Prasenjit Biswas
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2020 – today
- 2020
- [c15]Prasenjit Biswas, Sarit Pal, Sunil P. Khatri:
A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. ICICT 2020: 114-123
2010 – 2019
- 2017
- [c14]Prasenjit Biswas, D. M. H. Walker:
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. VLSID 2017: 141-146 - 2016
- [c13]Kamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas:
JU_KS_Group@FIRE 2016: Consumer Health Information Search. FIRE (Working Notes) 2016: 208-213 - [i1]Kamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas:
JU_KS_Group@FIRE 2016: Consumer Health Information Search. CoRR abs/1612.08178 (2016) - 2010
- [c12]Prasenjit Biswas, Pramod P. Udupa
, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166 - [c11]Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2000 – 2009
- 2009
- [j11]Mythri Alle, Keshavan Varadarajan, Alexander Fell
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9(2): 11:1-11:48 (2009) - [c10]Alexander Fell
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136 - [c9]Alexander Fell
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC 2009: 251-254 - 2000
- [j10]Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama:
SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20(4): 28-39 (2000)
1990 – 1999
- 1997
- [c8]Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama:
Functional verification of the superscalar SH-4 microprocessor. COMPCON 1997: 115-120 - 1995
- [j9]Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas:
SH3: high code density, low power. IEEE Micro 15(6): 11-19 (1995) - 1994
- [j8]Surapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas:
Cut and Side-Effects in a Data-Driven Implementation of Prolog. New Gener. Comput. 12(3): 223-250 (1994) - 1993
- [j7]Dagung Lu, Prasenjit Biswas:
An extended scheduling technique for software pipelining. Microprocess. Microprogramming 37(1-5): 99-103 (1993) - [c7]Behrooz A. Shirazi, Krishna M. Kavi, Ali R. Hurson, Prasenjit Biswas:
PARSA: A Parallel Program Scheduling and Assessment Environment. ICPP (2) 1993: 68-72 - 1992
- [j6]Syhy-Chang Su, Prasenjit Biswas:
A memory-mapped interprocessor communication architecture using FIFO RAMs. Microprocess. Microprogramming 34(1-5): 187-191 (1992) - 1991
- [j5]Gautam Dewan, Prasenjit Biswas:
A snooping cache coherency protocol for hierarchically organized multiprocessors. Microprocessing and Microprogramming 31(1-5): 105-111 (1991) - [c6]Surapong Auwatanamongkol, Prasenjit Biswas:
A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs. ICPP (1) 1991: 17-20 - 1990
- [j4]Shyh-Chang Su, Prasenjit Biswas:
Scheduling demand-driven parallel logic programs on transputers. Microprocessing and Microprogramming 28(1-5): 37-41 (1990) - [j3]Prasenjit Biswas, Jin Chen:
A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines. Microprocessing and Microprogramming 28(1-5): 161-166 (1990)
1980 – 1989
- 1989
- [c5]Chin-Feng Fan, Prasenjit Biswas:
Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programs. TAI 1989: 685-692 - 1988
- [c4]Prasenjit Biswas, Chien-Chao Tseng:
LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs. FGCS 1988: 1059-1070 - [c3]Prasenjit Biswas, Shyh-Chang Su, David Y. Y. Yun:
A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs. ICLP/SLP 1988: 1160-1179 - [c2]Chien-Chao Tseng, Prasenjit Biswas:
A Data-Driven Parallel Execution Model for Logic Programs. ICLP/SLP 1988: 1204-1222 - [c1]Prasenjit Biswas, Arun K. Majumdar:
A Fuzzy Hybrid Model for Pattern Classification. Pattern Recognition 1988: 183-192 - 1985
- [j2]Prasenjit Biswas, Subrata Dasgupta:
Architectural support for variable addressing in Ada - A design approach. Int. J. Parallel Program. 14(1): 51-72 (1985) - 1983
- [j1]Prasenjit Biswas, Arun K. Majumdar:
A supervised learning algorithm for hierarchical classification of fuzzy patterns. Inf. Sci. 31(2): 91-106 (1983)
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