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Yoshiki Saito
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2010 – 2019
- 2012
- [c12]Akiko Tanaka, Katsuto Uehara, Toru Tamura, Yoshiki Saito
:
Area change detection in river mouthbars at the Mekong River delta using Synthetic Aperture Radar (SAR) data. IGARSS 2012: 4911-4914 - 2011
- [j1]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [c11]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c10]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - 2010
- [c9]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano:
MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC 2010: 377-378 - [c8]Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT 2010: 349-352
2000 – 2009
- 2009
- [c7]Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano:
Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182 - [c6]Toru Sano, Yoshiki Saito, Hideharu Amano:
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA 2009: 112-118 - [c5]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA 2009: 283-286 - [c4]Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano:
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL 2009: 530-533 - [c3]Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano:
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT 2009: 104-111 - 2008
- [c2]Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310 - [c1]Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332
Coauthor Index
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