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Davide Marano
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2020 – today
- 2022
- [j11]Alfio Dario Grasso
, Davide Marano
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review. Int. J. Circuit Theory Appl. 50(5): 1462-1486 (2022)
2010 – 2019
- 2018
- [j10]Alfio Dario Grasso
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of CL. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1529-1533 (2018) - [c15]Alfio Dario Grasso
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW. ICICDT 2018: 37-40 - 2017
- [c14]Davide Marano
Novel straightforward and effective extraction methodology for SiPM model parameters. ECCTD 2017: 1-4 - 2016
- [j9]Alfio Dario Grasso
Symbolic factorization methodology for multistage amplifier transfer functions. Int. J. Circuit Theory Appl. 44(1): 38-59 (2016) - [j8]Davide Marano
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1349-1359 (2016) - [c13]Davide Marano
Enhanced analytical model and output dynamic response of SiPM-Based electronic read-outs. ICECS 2016: 305-308 - [c12]Davide Marano
A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW. ICECS 2016: 728-731 - 2015
- [j7]Alfio Dario Grasso
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1453-1462 (2015) - [c11]Alfio Dario Grasso
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2. ICECS 2015: 65-68 - [c10]Davide Marano
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors. NEWCAS 2015: 1-4 - 2014
- [j6]Alfio Dario Grasso
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 663-670 (2014) - [c9]Davide Marano
A new accurate analytical expression for the SiPM transient response to single photons. ICECS 2014: 514-517 - 2011
- [c8]Davide Marano
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. ISCAS 2011: 29-32 - 2010
- [j5]Davide Marano
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads. IET Circuits Devices Syst. 4(2): 87-98 (2010) - [j4]Alfio Dario Grasso
Analytical comparison of reversed nested Miller frequency compensation techniques. Int. J. Circuit Theory Appl. 38(7): 709-737 (2010) - [j3]Davide Marano
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications. J. Circuits Syst. Comput. 19(2): 325-334 (2010) - [c7]Davide Marano
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. ISCAS 2010: 777-780 - [c6]Davide Marano
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. ISCAS 2010: 2816-2819 - [c5]Davide Marano
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. ISCAS 2010: 2832-2835
2000 – 2009
- 2009
- [j2]Davide Marano
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers. J. Circuits Syst. Comput. 18(7): 1321-1331 (2009) - [c4]Davide Marano
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs. ICECS 2009: 128-131 - [c3]Davide Marano
A high-speed low-power output buffer amplifier for large-size LCD applications. ICECS 2009: 132-135 - [c2]Davide Marano
Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications. ISCAS 2009: 1949-1952 - [c1]Davide Marano
A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers. ISCAS 2009: 2725-2728 - 2007
- [j1]Alfio Dario Grasso
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 382-386 (2007)
Coauthor Index
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