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Takao Marukame
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2020 – today
- 2020
- [c9]Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi:
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c8]Takao Marukame, Toshimitsu Kitamura, Junichi Sugino, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Yoshifumi Nishi:
Live Demonstration: Low-Power Static Neural Network Circuits for Long-Term Change Detection. ISCAS 2019: 1 - [c7]Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi:
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. ISCAS 2019: 1-5 - 2018
- [c6]Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi:
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS 2018: 1-5 - [c5]Takao Marukame, Yutaka Tamura, Koji Takahashi, Toshimitsu Kitamura, Takashi Takebayashi, Yoshifumi Nishi:
Live Demonstration: A prototype of Analog/Digital-mixed Neural Networks for reconfigurable learning. ISCAS 2018: 1- - 2017
- [j1]Takao Marukame, Kodai Ueyoshi, Tetsuya Asai
, Masato Motomura
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 462-466 (2017) - [c4]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS 2017: 1 - [i2]Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani:
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR abs/1703.00073 (2017) - 2016
- [c3]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS 2016: 357-360 - [c2]Takao Marukame, Alexandre Schmid
Bit-flipping LDPC under noise conditions and its application to physically unclonable functions. ISCAS 2016: 1114-1117 - 2011
- [i1]Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito:
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET. CoRR abs/1104.1493 (2011)
2000 – 2009
- 2007
- [c1]Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto:
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. ISMVL 2007: 49
Coauthor Index
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