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Shlomo Weiss
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2020 – today
- 2021
- [j44]Junyi Zhou, Roger Kahn
, Shlomo Weiss
A novel low power hybrid cache using GC-EDRAM cells. Integr. 81: 234-245 (2021) - 2020
- [j43]David Uzan, Roger Kahn, Shlomo Weiss:
Perceptron based filtering of futile prefetches in embedded VLIW DSPs. J. Syst. Archit. 110: 101826 (2020)
2010 – 2019
- 2018
- [j42]Konstantin Berestizshevsky
Decoupled Branch Predictor for Embedded DSP. IEEE Embed. Syst. Lett. 10(3): 57-60 (2018) - [j41]Ben Perach
SiMT-DSP: A Massively Multithreaded DSP Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1413-1426 (2018) - 2016
- [j40]Gadi Oxman
Deflection Routing in Hierarchical Mesh NoCs. IEEE Embed. Syst. Lett. 8(2): 45-48 (2016) - [j39]Gadi Oxman, Shlomo Weiss:
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1667-1680 (2016) - 2015
- [c21]Gadi Oxman, Shlomo Weiss:
DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator. ISPASS 2015: 193-202 - 2014
- [j38]Gadi Oxman, Shlomo Weiss:
RIDER: Ring deflection router with buffers. Des. Autom. Embed. Syst. 18(3-4): 141-155 (2014) - [j37]Doron Sabo, Oded Barzelay, Shlomo Weiss, Miriam Furst:
Fast evaluation of a time-domain non-linear cochlear model on GPUs. J. Comput. Phys. 265: 97-112 (2014) - [j36]Gadi Oxman, Shlomo Weiss, Yair Be'ery
Computational methods for Conway's Game of Life cellular automaton. J. Comput. Sci. 5(1): 24-31 (2014) - [j35]Sagi Manole, Amit Golander, Shlomo Weiss:
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators. IEEE Trans. Computers 63(2): 448-460 (2014) - [j34]Alexei Jolondz, Shlomo Weiss, Amit Golander:
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2206-2210 (2014) - 2013
- [j33]Omer Zilberberg, Shlomo Weiss, Sivan Toledo:
Phase-change memory: An architectural perspective. ACM Comput. Surv. 45(3): 29:1-29:33 (2013) - [j32]Eran Shifer, Shlomo Weiss:
Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores. ACM Trans. Archit. Code Optim. 10(3): 10:1-10:25 (2013) - [c20]Doron Sabo, Shlomo Weiss, Miriam Furst:
A Parallel Algorithm for a Physiological Non-Linear Model of the Cochlea. ICCS 2013: 682-691 - 2012
- [j31]Gal Motika, Shlomo Weiss:
Virtio network paravirtualization driver: Implementation and performance of a de-facto standard. Comput. Stand. Interfaces 34(1): 36-47 (2012) - [j30]Simon Grinberg, Shlomo Weiss:
Architectural virtualization extensions: A systems perspective. Comput. Sci. Rev. 6(5-6): 209-224 (2012) - [j29]Nadav Cohen, Shlomo Weiss:
Complex Floating Point - A Novel Data Word Representation for DSP Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2252-2262 (2012) - [c19]Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
Streamlined Network-on-Chip for Multicore Embedded Architectures. ARCS 2012: 238-249 - [c18]Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
Buffered deflection routing for networks-on-chip. INA-OCMC@HiPEAC 2012: 9-12 - 2010
- [j28]Roger Kahn, Shlomo Weiss:
Reducing leakage power with BTB access prediction. Integr. 43(1): 49-57 (2010) - [j27]Nadav Levison, Shlomo Weiss:
Branch target buffer design for embedded processors. Microprocess. Microsystems 34(6): 215-227 (2010) - [c17]Nadav Levison, Shlomo Weiss:
Low power branch prediction for embedded application processors. ISLPED 2010: 67-72
2000 – 2009
- 2009
- [j26]Ron Gabor, Avi Mendelson, Shlomo Weiss:
Service level agreement for multithreaded processors. ACM Trans. Archit. Code Optim. 6(2): 6:1-6:33 (2009) - [j25]Amit Golander, Shlomo Weiss:
Checkpoint allocation and release. ACM Trans. Archit. Code Optim. 6(3): 10:1-10:27 (2009) - [j24]Amit Golander, Shlomo Weiss, Ronny Ronen:
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 474-478 (2009) - [j23]Amit Golander, Shlomo Weiss:
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2: 242-268 (2009) - 2008
- [j22]Amit Golander, Shlomo Weiss, Ronny Ronen:
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7(2): 65-68 (2008) - [j21]Roger Kahn, Shlomo Weiss:
Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers. Microprocess. Microsystems 32(8): 425-436 (2008) - [j20]Amit Golander, Shlomo Weiss:
Hiding the misprediction penalty of a resource-efficient high-performance processor. ACM Trans. Archit. Code Optim. 4(4): 6:1-6:32 (2008) - 2007
- [j19]Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness enforcement in switch on event multithreading. ACM Trans. Archit. Code Optim. 4(3): 15 (2007) - 2006
- [j18]Yehuda Sadeh Weinraub, Shlomo Weiss:
Power-aware out-of-order issue logic in high-performance microprocessors. Microprocess. Microsystems 30(7): 457-467 (2006) - [c16]Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness and Throughput in Switch on Event Multithreading. MICRO 2006: 149-160 - 2004
- [j17]Tomer Karin, Shlomo Weiss:
Programming Windows NT device drivers to operate non-interrupting embedded devices. Microprocess. Microsystems 28(1): 27-35 (2004) - [c15]Doron Nakar, Shlomo Weiss:
Selective main memory compression by identifying program phase changes. WMPI 2004: 96-101 - 2003
- [j16]Shlomo Weiss, Roman Tsikel:
Approximate prefix coding for system-on-a-chip programs. J. Syst. Archit. 48(13-15): 367-375 (2003) - [j15]Shlomo Weiss, Shay Beren:
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors. IEEE Trans. Computers 52(11): 1495-1500 (2003) - [j14]Tal Oved, Shlomo Weiss:
Embedded instruction memory in automotive engine controllers. IEEE Trans. Veh. Technol. 52(1): 173-183 (2003) - [c14]Avishay Orpaz, Shlomo Weiss:
Pattern Matching by means of Multi-Resolution Compression. DCC 2003: 441 - 2002
- [j13]Ehud Finkelstein, Shlomo Weiss:
A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations. J. Syst. Archit. 47(9): 807-819 (2002) - [c13]Avishay Orpaz, Shlomo Weiss:
A study of CodePack: optimizing embedded code space. CODES 2002: 103-108 - 2001
- [c12]Shlomo Weiss, Shay Beren:
HW/SW partitioning of an embedded instruction memory decompressor. CODES 2001: 36-41
1990 – 1999
- 1999
- [j12]Shlomo Weiss, Ehud Finkelstein:
Extending PCI Performance Beyond the Desktop. Computer 32(6): 80-87 (1999) - [j11]Ehud Finkelstein, Shlomo Weiss:
Microprocessor system buses: A case study. J. Syst. Archit. 45(12-13): 1151-1168 (1999) - 1998
- [j10]Shlomo Weiss, A. Goldstein:
Floating point micropipeline performance. J. Syst. Archit. 45(1): 15-29 (1998) - [j9]Shlomo Reches, Shlomo Weiss:
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes. IEEE Trans. Computers 47(8): 907-912 (1998) - [c11]Eitan Federovsky, Meir Feder, Shlomo Weiss:
Branch Prediction Based on Universal Data Compression Algorithms. ISCA 1998: 62-72 - 1997
- [c10]Shlomo Reches, Shlomo Weiss:
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes. International Conference on Supercomputing 1997: 285-292 - 1995
- [c9]Shlomo Weiss:
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. HPCA 1995: 14-21 - 1994
- [j8]James E. Smith, Shlomo Weiss:
PowerPC 601 and Alpha 21064: A Tale of Two RISCs. Computer 27(6): 46-58 (1994) - 1993
- [j7]Shlomo Weiss:
Optimizing a superscalar machine to run vector code. IEEE Parallel Distributed Technol. Syst. Appl. 1(2): 73-83 (1993) - 1992
- [j6]Shlomo Weiss:
Memory conflict resolution in vector supercomputers. J. Supercomput. 6(1): 71-85 (1992) - [j5]Ravi Ganesan, Shlomo Weiss:
Scalar Memory References in Pipelined Multiprocessors: A Performance Study. IEEE Trans. Software Eng. 18(1): 78-86 (1992) - 1991
- [c8]Shlomo Weiss:
Multiple-Port Memory Access in Decoupled Architecture Processors. ICPP (1) 1991: 373-376 - 1990
- [j4]Shlomo Weiss, James E. Smith:
A study of scalar compilation techniques for pipelined supercomputers. ACM Trans. Math. Softw. 16(3): 223-245 (1990)
1980 – 1989
- 1989
- [j3]Shlomo Weiss:
Scalar supercomputer architecture. Proc. IEEE 77(12): 1970-1982 (1989) - [c7]Shlomo Weiss:
An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors. ISCA 1989: 380-386 - 1987
- [c6]Shlomo Weiss, James E. Smith:
A Study of Scalar Compilation Techniques for Pipelined Supercomputers. ASPLOS 1987: 105-109 - 1986
- [j2]James E. Smith, Shlomo Weiss, Nicholas Y. Pang:
A Simulation Study of Decoupled Architecture Computers. IEEE Trans. Computers 35(8): 692-702 (1986) - [c5]Shlomo Weiss, Katie Rotzell, Tom Rhyne, Arny Goldfein:
DOSS: a storage system for design data. DAC 1986: 41-47 - 1984
- [j1]Shlomo Weiss, James E. Smith:
Instruction Issue Logic in Pipelined Supercomputers. IEEE Trans. Computers 33(11): 1013-1022 (1984) - [c4]Shlomo Weiss:
Recovery of In-Memory Data Structures for Interactive Update Applications. COMPCON 1984: 335-338 - [c3]Randy H. Katz, Shlomo Weiss:
Design transaction management. DAC 1984: 692-693 - [c2]Shlomo Weiss, James E. Smith:
Instruction Issue Logic for Pipelined Supercomputers. ISCA 1984: 110-118 - 1983
- [c1]Randy H. Katz, Shlomo Weiss:
Chip assemblers: Concepts and capabilities. DAC 1983: 25-30
Coauthor Index
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