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Matt Grange
2010 – 2019
- 2015
- [j1]Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa:
Zero-load predictive model for performance analysis in deflection routing NoCs. Microprocess. Microsystems 39(8): 634-647 (2015) - 2013
- [c8]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen:
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 3DIC 2013: 1-5 - 2011
- [c7]Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa:
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD 2011: 310-317 - [c6]Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion:
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS 2011: 57-64 - [c5]Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch:
3-D integration and the limits of silicon computation. VLSI-SoC 2011: 343-348 - [p1]Axel Jantsch, Matthew Grange, Dinesh Pamunuwa:
The Promises and Limitations of 3-D Integration. 3D Integration for NoC-based SoC Architectures 2011: 27-44 - 2010
- [c4]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen:
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE 2010: 1325-1328
2000 – 2009
- 2009
- [c3]Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen:
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 - [c2]Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng:
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC 2009: 1-8 - [c1]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen:
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123
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