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Manuel Delgado-Restituto
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- affiliation: University of Seville, Spain
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2020 – today
- 2022
- [j30]David Palomeque-Mangut
, Ángel Rodríguez-Vázquez
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process. Sensors 22(17): 6429 (2022) - [c41]David Palomeque-Mangut, Ángel Rodríguez-Vázquez, Manuel Delgado-Restituto
Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process. BioCAS 2022: 335-339 - [c40]David Palomeque-Mangut
A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process. LASCAS 2022: 1-4 - [c39]David Palomeque-Mangut
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils. PRIME 2022: 325-328 - 2021
- [j29]Norberto Pérez-Prieto
A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System. IEEE Trans. Biomed. Circuits Syst. 15(5): 960-977 (2021) - [c38]Norberto Pérez-Prieto, Ángel Rodríguez-Vázquez, Manuel Delgado-Restituto
Spatial Encoding Techniques in Time-Multiplexed Neural Recording Front-Ends. NEWCAS 2021: 1-4 - 2020
- [j28]Rafaella Fiorelli
Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction. IEEE Trans. Biomed. Circuits Syst. 14(3): 606-619 (2020) - [j27]Rafaella Fiorelli
Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 47-51 (2020) - [j26]José Luis Valtierra
A Sub- $\mu$ W Reconfigurable Front-End for Invasive Neural Recording That Exploits the Spectral Characteristics of the Wideband Neural Signal. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1426-1437 (2020)
2010 – 2019
- 2019
- [j25]Manuel Delgado-Restituto
Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation. IEEE Trans. Biomed. Circuits Syst. 13(5): 957-970 (2019) - [c37]Norberto Pérez-Prieto, Rafaella Fiorelli, José Luis Valtierra, Pablo Pérez-García
A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression. BioCAS 2019: 1-4 - [c36]José Luis Valtierra, Rafaella Fiorelli, Norberto Pérez-Prieto, Manuel Delgado-Restituto
A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation. BioCAS 2019: 1-4 - [c35]Norberto Pérez-Prieto, Manuel Delgado-Restituto
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications. ISCAS 2019: 1-5 - [c34]Norberto Pérez-Prieto, José Luis Valtierra, Manuel Delgado-Restituto
A Sub-μVRms Chopper Front-End for ECoG Recording. ISCAS 2019: 1-5 - [c33]José Luis Valtierra, Rafaella Fiorelli, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez:
A Sub-µW Reconfigurable Front-End for Invasive Neural Recording. LASCAS 2019: 85-88 - 2018
- [j24]Juan Antonio Leñero-Bardallo
Asynchronous Spiking Pixel With Programmable Sensitivity to Illumination. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3854-3863 (2018) - 2017
- [j23]Manuel Delgado-Restituto
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor. IEEE Trans. Biomed. Circuits Syst. 11(2): 420-433 (2017) - [j22]Manuel Delgado-Restituto
Guest Editorial - Special Issue on Selected Papers From IEEE BioCAS 2016. IEEE Trans. Biomed. Circuits Syst. 11(6): 1256-1257 (2017) - [c32]Norberto Pérez-Prieto, Manuel Delgado-Restituto
A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation. ECCTD 2017: 1-4 - [c31]José Luis Valtierra, Manuel Delgado-Restituto
A 2.2 μW analog front-end for multichannel neural recording. LASCAS 2017: 1-4 - 2016
- [c30]Manuel Delgado-Restituto
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications. APCCAS 2016: 421-424 - [c29]Manuel Delgado-Restituto
Mixed-signal quadratic operators for the feature extraction of neural signals. BioCAS 2016: 368-371 - 2015
- [j21]Jesús Ruiz-Amaya, Alberto Rodríguez-Pérez
A Low Noise Amplifier for Neural Spike Recording Interfaces. Sensors 15(10): 25313-25335 (2015) - [c28]James Brian Romaine
Hardware friendly algorithm for the calculation of phase synchronization between neural signals. BioCAS 2015: 1-4 - 2014
- [j20]Alberto Rodríguez-Pérez
A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces. IEEE Trans. Biomed. Circuits Syst. 8(3): 358-370 (2014) - [c27]Alberto Rodríguez-Pérez
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration. A-SSCC 2014: 205-208 - [c26]Alberto Rodríguez-Pérez
Self-calibration of neural recording sensors. BioCAS 2014: 663-666 - [c25]Manuel Delgado-Restituto
In vivo measurements with a 64-channel extracellular neural recording integrated circuit. ICECS 2014: 486-489 - [c24]Manuel Carrasco-Robles
Mixed-signal energy feature extractor of EEG frequency bands. LASCAS 2014: 1-4 - 2013
- [j19]Jens Masuch, Manuel Delgado-Restituto
Low-power quadrature generators for body area network applications. Int. J. Circuit Theory Appl. 41(1): 33-43 (2013) - [j18]Alberto Rodríguez-Pérez, Manuel Delgado-Restituto
Impact of parasitics on even symmetric split-capacitor arrays. Int. J. Circuit Theory Appl. 41(9): 972-987 (2013) - [j17]Jens Masuch, Manuel Delgado-Restituto
Co-Integration of an RF Energy Harvester Into a 2.4 GHz Transceiver. IEEE J. Solid State Circuits 48(7): 1565-1574 (2013) - [c23]Onur Kazanc, Jose A. Rodríguez-Rodríguez, Manuel Delgado-Restituto
Far-field UHF remotely powered front-end for patient monitoring with wearable antenna. NEWCAS 2013: 1-4 - 2012
- [j16]Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
IC-constrained optimization of continuous-time Gm-C filters. Int. J. Circuit Theory Appl. 40(2): 127-143 (2012) - [j15]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
Behavioral modeling of pipeline ADC building blocks. Int. J. Circuit Theory Appl. 40(6): 571-594 (2012) - [j14]Jens Masuch, Manuel Delgado-Restituto
A 190-µW zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC. IEEE J. Solid State Circuits 47(11): 2796-2806 (2012) - [j13]Alberto Rodríguez-Pérez
A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression. IEEE Trans. Biomed. Circuits Syst. 6(2): 87-100 (2012) - [j12]Jose Antonio Rodríguez-Rodríguez, Manuel Delgado-Restituto
An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders. IEEE Trans. Ind. Electron. 59(2): 1310-1322 (2012) - [c22]Alberto Rodríguez-Pérez
A 64-channel inductively-powered neural recording sensor array. BioCAS 2012: 228-231 - [c21]Jens Masuch, Manuel Delgado-Restituto
An RF energy harvester with supply management for co-integration into a 2.4 GHz transceiver. ESSCIRC 2012: 113-116 - [c20]Jens Masuch, Manuel Delgado-Restituto
An RF-to-DC energy harvester for co-integration in a low-power 2.4 GHz transceiver frontend. ISCAS 2012: 680-683 - 2011
- [j11]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2816-2828 (2011) - [c19]Alberto Rodríguez-Pérez
A power efficient neural spike recording channel with data bandwidth reduction. ISCAS 2011: 1704-1707 - 2010
- [c18]Jens Masuch, Manuel Delgado-Restituto
Transformer based front-end for a low power 2.4 GHz transceiver. APCCAS 2010: 288-291 - [c17]Jens Masuch, Manuel Delgado-Restituto
Low power 2.4 GHz quadrature generation for body area network applications. ISCAS 2010: 493-496
2000 – 2009
- 2009
- [j10]Manuel Delgado-Restituto
ECCTD 2007 Special Issue 'Bridging Technology Innovations to Foundations'. Int. J. Circuit Theory Appl. 37(2): 159-161 (2009) - [j9]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1077-1087 (2009) - [c16]Jens Masuch, Manuel Delgado-Restituto
Design constraints for the inductive power and data link of an implanted body sensor. ECCTD 2009: 425-428 - 2008
- [j8]Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
Matrix Methods for the Dynamic Range Optimization of Continuous-Time Gm- C Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2525-2538 (2008) - [c15]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
Electrical-level synthesis of pipeline ADCs. APCCAS 2008: 1628-1631 - [c14]Alberto Rodríguez-Pérez
An ultra-low power consumption 1-V, 10-bit succesive approximation ADC. ICECS 2008: 634-637 - 2007
- [c13]Davide Brandano, Manuel Delgado-Restituto
A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology. ECCTD 2007: 72-75 - [c12]Jesús Ruiz-Amaya, Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits. ECCTD 2007: 452-455 - 2006
- [c11]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. APCCAS 2006: 1671-1674 - 2005
- [j7]Manuel Delgado-Restituto
A mixed-signal integrated circuit for FM-DCSK modulation. IEEE J. Solid State Circuits 40(7): 1460-1471 (2005) - [c10]Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
Dynamic range optimization of continuous-time Gm-C filters. ECCTD 2005: 205-208 - [c9]Juan Francisco Fernández-Bootello, Manuel Delgado-Restituto
A 0.18µm CMOS low-noise elliptic low-pass continuous-time filter. ISCAS (1) 2005: 800-803 - [c8]Manuel Delgado-Restituto
An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology. ISCAS (5) 2005: 4626-4629 - [c7]Jesús Ruiz-Amaya, José M. de la Rosa, Manuel Delgado-Restituto
Behavioral modeling simulation and high-level synthesis of pipeline A/D converters. ISCAS (6) 2005: 5609-5612 - 2004
- [j6]Rocío del Río
Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 47-62 (2004) - [c6]Manuel Delgado-Restituto, A. J. Acosta, Ángel Rodríguez-Vázquez:
A mixed-signal integrated circuit for FM-DCSK modulation. ESSCIRC 2004: 331-334 - 2003
- [j5]Oscar Guerra
A modem in CMOS technology for data communication on the low-voltage power line. Integr. 36(4): 229-236 (2003) - 2002
- [j4]Manuel Delgado-Restituto
Integrated chaos generators. Proc. IEEE 90(5): 747-767 (2002) - 2001
- [c5]Rafael Castro-López
Retargeting of mixed-signal blocks for SoCs. DATE 2001: 772-775
1990 – 1999
- 1999
- [j3]Ángel Rodríguez-Vázquez, Elisenda Roca
MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips. J. VLSI Signal Process. 23(2-3): 239-266 (1999) - [c4]José E. Franca, Nuno Horta
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design. ICECS 1999: 1679-1683 - 1998
- [c3]Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez, Veikko Porra:
Design considerations for a linear modulation DCSK chaos-based radio. ICECS 1998: 239-242 - 1995
- [c2]Manuel Delgado-Restituto, Rafael López-Ahumada, Ángel Rodríguez-Vázquez:
Secure Communication Through Switched-Current Chaotic Circuits. ISCAS 1995: 2237-2240 - 1994
- [j2]Ángel Rodríguez-Vázquez, Manuel Delgado-Restituto
Generation of Chaotic Signals Using Current-Mode Techniques. J. Intell. Fuzzy Syst. 2(1): 15-37 (1994) - [c1]Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez:
CMOS Current-Mode Chaotic Neurons. ISCAS 1994: 499-502 - 1993
- [j1]Manuel Delgado-Restituto
A CMOS monolithic Chua's Circuit. J. Circuits Syst. Comput. 3(2): 259-268 (1993) - [p1]Manuel Delgado-Restituto
A CMOS monolithic Chua's Circuit. Chua's Circuit 1993: 13-24
Coauthor Index
[j30] [c41] [c40] [c39] [j29] [c38] [j28] [j27] [j26] [j25] [c37] [c36] [c35] [c34] [c33] [j24] [j23] [c32] [c31] [c30] [c29] [c27] [c26] [c25] [j16] [j15] [j13] [j12] [c22] [j11] [c19] [c18] [j10] [j9] [j8] [c15] [c13] [j7] [c10] [c9] [c8] [c7] [j6] [c6] [j5] [j4] [c5] [j3] [c4] [c3] [c2] [j2] [c1] [j1]
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