default search action
Masanori Furuta
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2022
- [j17]Zhaoqi Chen
, Alia Nasrallah, Milad Alemohammad, Masanori Furuta, Ralph Etienne-Cummings
Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation. Neuromorph. Comput. Eng. 2(4): 44013 (2022) - 2021
- [c21]Masanori Furuta, Koichiro Ban, Daisuke Kobayashi, Tomoyuki Shibata:
An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention. MWSCAS 2021: 321-325 - 2020
- [c20]Alia Nasrallah, Zhaoqi Chen, Milad Alemohammad, Adyant Balaji, Adam B. Cellon, Masanori Furuta, Ralph Etienne-Cummings:
Velocity-Tuned Oscillators for NeuroSLAM and Spatial Navigation. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j16]Kentaro Yoshioka
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2575-2586 (2019) - [c19]Adam B. Cellon, Adebayo A. Eisape, Masanori Furuta, Ralph Etienne-Cummings:
Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware. ISCAS 2019: 1-5 - 2017
- [c18]Kentaro Yoshioka
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC 2017: 478-479 - 2016
- [j15]Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo:
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(2): 547-554 (2016) - [j14]Akihide Sai
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 3125-3136 (2016) - [c17]Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura:
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS 2016: 482-485 - [c16]Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura:
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC 2016: 122-123 - [c15]Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura:
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC 2016: 336-337 - [c14]Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura:
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC 2016: 436-437 - 2015
- [j13]Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura:
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 492-499 (2015) - [c13]Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura:
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS 2015: 357-360 - 2014
- [c12]Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura:
A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS 2014: 1151-1154 - [c11]Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura:
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC 2014: 348-349 - 2013
- [j12]Masanori Furuta, Ippei Akita
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1552-1561 (2013) - [j11]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1113-1121 (2013) - [c10]Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura:
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT 2013: 1-4 - 2012
- [c9]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS 2012: 1050-1053 - 2011
- [j10]Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits 46(6): 1360-1370 (2011) - [c8]Ippei Akita
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC 2011: 293-296 - 2010
- [c7]Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. ISSCC 2010: 382-383
2000 – 2009
- 2008
- [c6]Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
An area-efficient sampling rate converter using negative feedback technique. ISCAS 2008: 1922-1925 - 2007
- [j9]Jong-Ho Park, Shoji Kawahito, Masanori Furuta, Masaaki Sasaki, Yasuo Wakamori, Mitsuhito Mase, Yukihiro Ohta:
A Wide Dynamic Range CMOS Image Sensor with Improved 12-bit Column Parallel Cyclic ADCs. Inf. Media Technol. 2(3): 695-703 (2007) - [j8]Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura:
Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors. Inf. Media Technol. 2(3): 704-712 (2007) - [j7]Kazutaka Honda, Masanori Furuta, Shoji Kawahito:
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. IEEE J. Solid State Circuits 42(4): 757-765 (2007) - [j6]Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito:
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. IEEE J. Solid State Circuits 42(4): 766-774 (2007) - [j5]Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki:
A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. 56(6): 2301-2311 (2007) - [c5]Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura:
A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits. CICC 2007: 833-836 - 2006
- [j4]Zheng Liu, Masanori Furuta, Shoji Kawahito:
Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits. IEICE Trans. Electron. 89-C(6): 710-716 (2006) - [c4]Kazutaka Honda, Masanori Furuta, Shoji Kawahito:
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues. ISCAS 2006: 1031-1034 - 2005
- [j3]Shoji Kawahito, Kazutaka Honda, Masanori Furuta, Nobuhiro Kawai, Daisuke Miyazaki:
Low-Power Design of High-Speed A/D Converters. IEICE Trans. Electron. 88-C(4): 468-478 (2005) - [j2]Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta:
A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters. IEEE J. Solid State Circuits 40(12): 2787-2795 (2005) - [c3]Masanori Furuta, Shoji Kawahito, Toru Inoue, Yukinari Nishikawa:
A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors. ESSCIRC 2005: 411-414 - 2003
- [j1]Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta:
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture. IEEE J. Solid State Circuits 38(2): 369-373 (2003) - [c2]Daisuke Miyazaki, Masanori Furuta, Shoji Kawahito:
A 75mW 10bit 120MSample/s parallel pipeline ADC. ESSCIRC 2003: 719-722 - [c1]Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta:
A digitally skew correctable multi-phase clock generator using a master-slave DLL. ISCAS (1) 2003: 105-108
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-28 22:27 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: