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Dariusz Koscielnik
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2020 – today
- 2023
- [j7]Konrad Jurasz, Dariusz Koscielnik, Jakub Szyduczynski, Witold Machowski:
A New Successive Time Balancing Time-to-Digital Conversion Method. Sensors 23(24): 9712 (2023) - 2021
- [j6]Konrad Jurasz, Dariusz Koscielnik, Jakub Szyduczynski, Marek Miskowicz:
Systematization and Comparison of the Binary Successive Approximation Variants. Sensors 21(24): 8267 (2021) - 2020
- [c20]Jakub Szyduczynski, Dariusz Koscielnik, Konrad Jurasz, Marek Miskowicz:
Successive Approximation Time-to-Digital Converters. EBCCSP 2020: 1-7
2010 – 2019
- 2019
- [j5]Jakub Szyduczynski, Dariusz Koscielnik, Marek Miskowicz:
A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements. Sensors 19(5): 1109 (2019) - [c19]Jakub Szyduczynski, Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski, Dariusz Koscielnik, Marek Miskowicz:
Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization. EBCCSP 2019: 1-9 - 2018
- [j4]Dominik Rzepka, Marek Miskowicz, Dariusz Koscielnik, Nguyen T. Thao:
Reconstruction of Signals From Level-Crossing Samples Using Implicit Information. IEEE Access 6: 35001-35011 (2018) - 2017
- [j3]Dominik Rzepka, Miroslaw Pawlak, Dariusz Koscielnik, Marek Miskowicz:
Bandwidth Estimation From Multiple Level-Crossings of Stochastic Signals. IEEE Trans. Signal Process. 65(10): 2488-2502 (2017) - [c18]Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz:
Clockless signal-dependent compressive sensing of multitone signals using time encoding machine. EBCCSP 2017: 1-8 - [c17]Jakub Szyduczynski, Dariusz Koscielnik, Marek Miskowicz:
Dynamic equalization of logic delays in feedback-based successive approximation TDCs. EBCCSP 2017: 1-6 - 2016
- [j2]Dariusz Koscielnik, Dominik Rzepka, Jakub Szyduczynski:
Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 366-370 (2016) - [c16]Dariusz Koscielnik, Jakub Szyduczynski, Dominik Rzepka, Wojciech Andrysiewicz, Marek Miskowicz:
Optimized design of successive approximation time-to-digital converter with single set of delay lines. EBCCSP 2016: 1-8 - [c15]Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz, Nguyen T. Thao:
Signal recovery from level-crossing samples using projections onto convex sets. EBCCSP 2016: 1-6 - 2015
- [c14]Wojciech Andrysiewicz, Dariusz Koscielnik, Marek Miskowicz:
I2C hardware master serial interface for asynchronous ADCs. ISSE 2015: 77-81 - [c13]Marek Miskowicz, Jakub Szyduczynski, Dariusz Koscielnik:
Analytical approach to multiple memoryless backoff contention analysis. WFCS 2015: 1-4 - 2014
- [c12]Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz:
Recovery of varying-bandwidth signal for level-crossing sampling. ETFA 2014: 1-6 - 2013
- [c11]Dariusz Koscielnik, Marek Miskowicz:
Event-driven analog-to-digital converter with conversion-speed-centric architecture and activity-dependent power consumption. ETFA 2013: 1-6 - [c10]Dariusz Koscielnik, Marek Miskowicz, Jakub Szyduczynski:
Upper Bounds on Unsuccessful Transmission Rate in Persistent and Non-Persistent CSMA Protocols. ICCCN 2013: 1-5 - 2012
- [c9]Lukasz Plachno, Marcin Oleksiak, Dariusz Koscielnik, Marek Jableka:
I2C interface design for hardware master devices. PDeS 2012: 163-168 - 2011
- [c8]Dariusz Koscielnik, Marek Miskowicz, Marek Jableka:
Natural compression and expansion characteristics of asynchronous Sigma-Delta ADC. ICSPCS 2011: 1-8 - 2010
- [j1]Dariusz Koscielnik:
Simulation Study of the Influence of the Hidden and Exposed Stations for the Efficiency of IEEE 802.15.4 LR-WPAN Networks. Wirel. Sens. Netw. 2(1): 7-17 (2010) - [c7]Marek Miskowicz, Dariusz Koscielnik:
Modeling end-to-end reliability in best-effort networked embedded systems. ETFA 2010: 1-4 - [c6]Dariusz Koscielnik, Marek Miskowicz:
Evaluating Maximum Transmission Unreliability in Persistent CSMA Protocol. ICINCO (1) 2010: 182-186
2000 – 2009
- 2009
- [c5]Dariusz Koscielnik, Marek Miskowicz:
Designing Asynchronous Analog-to-digital Converter with I2C Interface. ETFA 2009: 1-4 - [c4]Dariusz Koscielnik, Marek Miskowicz:
Towards Asynchronous Signal Processing. ICINCO-SPSMC 2009: 178-183 - 2007
- [c3]Dariusz Koscielnik, Marek Miskowicz:
Designing Time-to-Digital Converter for Asynchronous ADCs. DDECS 2007: 275-280 - [c2]Dariusz Koscielnik:
The Structure of a Control Network Integrated with the S-bus of an ISDN Network. ICN 2007: 67 - 2006
- [c1]Dariusz Koscielnik:
Analysis of IEEE 802.11E Standard in Terms of Real Time Application Requirements. ICWMC 2006: 14
Coauthor Index
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