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Peter Pöchmüller
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2020 – today
- 2024
- [c8]Heguo Yin, Peter Poechmueller:
Semiconductor Application Fail Root Causes And Secure Test Remedy. ETS 2024: 1-6 - 2023
- [j5]Ranran Zhou
, Haozhe Wang, Peng Wang, Peter Poechmueller, Yong Wang
A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1970-1979 (2023) - 2022
- [j4]Ranran Zhou
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5182-5192 (2022)
1990 – 1999
- 1999
- [j3]Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman:
A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34(11): 1580-1588 (1999) - 1996
- [j2]Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31(4): 558-566 (1996) - [j1]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996) - 1993
- [b1]Peter Pöchmüller:
Algorithmische Synthesetransformationen und deren Anwendung auf programmierbare Architekturen in mechatronischen Systemen. Darmstadt University of Technology, Germany, 1993, pp. 1-192 - [c7]Peter Poechmueller, Manfred Glesner, Fang Longsen:
High-level synthesis transformations for programmable architectures. EURO-DAC 1993: 8-13 - 1992
- [c6]Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner:
High-level synthesis in a rapid-prototype environment for mechatronic systems. EURO-DAC 1992: 188-193 - [c5]Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen:
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. FPL 1992: 96-105 - 1991
- [c4]Peter Poechmueller, G. K. Sharma, Manfred Glesner:
A CAD tool for designing large, fault-tolerant VLSI arrays. Great Lakes Symposium on VLSI 1991: 132-137 - [c3]Peter Poechmueller, Manfred Glesner:
An approach for multilevel logic cell optimization in module generators. Great Lakes Symposium on VLSI 1991: 284-289 - [c2]Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner:
HADES-high-level architecture development and exploration system. Great Lakes Symposium on VLSI 1991: 342-343 - [c1]Peter Poechmueller, Manfred Glesner:
A New Approach for Designing Fault-Tolerant Array Processors. Fault-Tolerant Computing Systems 1991: 324-331
Coauthor Index
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