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Toshikazu Sekine
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2010 – 2019
- 2019
- [j8]Mei Han
, Yasuhiro Takahashi
Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express 16(17): 20190400 (2019) - 2017
- [c26]Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD 2017: 1-4 - [c25]Mei Han
Low power Adiabatic Logic based on 2PC2AL. ICICDT 2017: 1-4 - [c24]Yasuhiro Takahashi
Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES 2017: 110-113 - 2015
- [j7]Yasuhiro Takahashi
SPICE model of memristive device using Tukey window function. IEICE Electron. Express 12(5): 20150149 (2015) - [j6]Kazunari Kato, Yasuhiro Takahashi
Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express 12(20): 20150695 (2015) - [j5]Câncio Monteiro
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. 9(5): 362-369 (2015) - [c23]Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD 2015: 1-4 - [c22]Kazunari Kato, Yasuhiro Takahashi
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS 2015: 1-4 - 2014
- [c21]Câncio Monteiro
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS 2014: 121-124 - [c20]Kazunari Kato, Yasuhiro Takahashi
Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS 2014: 495-498 - [c19]Haruki Ogata, Yasuhiro Takahashi
Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS 2014: 627-630 - [c18]Kazunari Kato, Yasuhiro Takahashi
Two phase clocking subthreshold adiabatic logic. ISCAS 2014: 598-601 - [c17]Câncio Monteiro
An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. ISCAS 2014: 826-829 - [c16]Câncio Monteiro
Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS 2014: 21-24 - 2013
- [j4]Câncio Monteiro
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. 44(6): 496-503 (2013) - [c15]Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi:
An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD 2013: 1-4 - [c14]Câncio Monteiro
Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. ECCTD 2013: 1-4 - [c13]Câncio Monteiro
DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS 2013: 2581-2584 - [c12]Câncio Monteiro
Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP 2013: 732-736 - 2012
- [j3]Nazrul Anuar Nayan
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43(4): 244-249 (2012) - [c11]Yuki Urata, Yasuhiro Takahashi
A low-power sense amplifier for adiabatic memory using memristor. APCCAS 2012: 112-115 - [c10]Yasuhiro Takahashi
2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS 2012: 124-127 - [c9]Yasuhiro Takahashi
Power-saving analysis of adiabatic logic in subthreshold region. ISPACS 2012: 590-594 - 2011
- [c8]Hides Jamima, Yasuhiro Takahashi
Low-power adiabatic SRAM. ISPACS 2011: 1-4 - [c7]Câncio Monteiro
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS 2011: 1-5 - 2010
- [c6]Nazrul Anuar
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC 2010: 364-368
2000 – 2009
- 2009
- [c5]Nazrul Anuar
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD 2009: 65-68 - [c4]Kazunari Kato, Yasuhiro Takahashi
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS 2009: 124-127 - [c3]Nazrul Anuar
Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS 2009: 503-506 - [c2]Nazrul Anuar
Two phase clocked adiabatic static CMOS logic. SoC 2009: 83-86 - 2007
- [j2]Yasuhiro Takahashi
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(7): 1376-1383 (2007) - [j1]Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama:
VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. 90-C(10): 2002-2006 (2007) - 2006
- [c1]Yasuhiro Takahashi
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS 2006: 1484-1487
Coauthor Index
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