Machine Learning Adoption in Blockchain-Based Smart Applications.

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Shantanu Dutt Vinay Verma Vishal Suthar Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. 309-326 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2007.906992 db/journals/tcad/tcad27.html#DuttVS08

Vishal Suthar Shantanu Dutt Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. 1165-1170 2006 conf/date/2006p DATE https://doi.org/10.1109/DATE.2006.244017 https://doi.ieeecomputersociety.org/10.1109/DATE.2006.244017 http://dl.acm.org/citation.cfm?id=1131803 db/conf/date/date2006p.html#SutharD06 Shantanu Dutt Huan Ren Fenghua Yuan Vishal Suthar A network-flow approach to timing-driven incremental placement for ASICs. 375-382 2006 conf/iccad/2006 ICCAD https://doi.org/10.1145/1233501.1233577 https://doi.org/10.1109/ICCAD.2006.320061 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2006.320061 db/conf/iccad/iccad2006.html#DuttRYS06 Vishal Suthar Shantanu Dutt Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. 36-43 2006 conf/vts/2006 VTS https://doi.org/10.1109/VTS.2006.47 https://doi.ieeecomputersociety.org/10.1109/VTS.2006.47 db/conf/vts/vts2006.html#SutharD06 Vishal Suthar Shantanu Dutt High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. 78-83 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1057661.1057682 db/conf/glvlsi/glvlsi2005.html#SutharD05 Vinay Verma Shantanu Dutt Vishal Suthar Efficient on-line testing of FPGAs with provable diagnosabilities. 498-503 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996705 db/conf/dac/dac2004.html#VermaDS04 José Luis Arias-Gonzáles Vipul Bansal Shantanu Dutt Ch. Srinivasa Reddy Huan Ren Devendra Singh Devesh Pratap Singh Vinay Verma Fenghua Yuan