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John-David Wellman
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2020 – today
- 2024
- [c11]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - [i3]Joseph Zuckerman, John-David Wellman, Ajay Vanamali, Manish Shankar, Gabriele Tombesi, Karthik Swaminathan, Kevin Lee, Mohit Kapur, Robert Philhower, Pradip Bose, Luca P. Carloni:
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures. CoRR abs/2407.04182 (2024) - 2023
- [j5]Naorin Hossain
, Alper Buyuktosunoglu
SoCurity: A Design Approach for Enhancing SoC Security. IEEE Comput. Archit. Lett. 22(2): 105-108 (2023) - 2022
- [c10]Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC 2022: 269-272 - [c9]Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD 2022: 20:1-20:9 - [i2]Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose:
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs. CoRR abs/2203.13396 (2022) - 2021
- [j4]Aporva Amarnath
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles. IEEE Comput. Archit. Lett. 20(2): 82-85 (2021) - [c8]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - [c7]David Trilla, John-David Wellman, Alper Buyuktosunoglu, Pradip Bose:
NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators. MICRO 2021: 507-521 - 2020
- [i1]Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose:
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. CoRR abs/2007.14371 (2020)
2010 – 2019
- 2017
- [c6]Ramon Bertran
Very Low Voltage (VLV) Design. ICCD 2017: 601-604
2000 – 2009
- 2008
- [j3]Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves:
Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM J. Res. Dev. 52(3): 293-306 (2008) - 2003
- [c5]Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325 - 2000
- [j2]David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook:
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro 20(6): 26-44 (2000) - [c4]David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose:
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. PACS 2000: 126-136
1990 – 1999
- 1999
- [j1]Mayan Moudgill, John-David Wellman, Jaime H. Moreno:
Environment for PowerPC microarchitecture exploration. IEEE Micro 19(3): 15-25 (1999) - 1996
- [b1]John-David Wellman:
Processor modeling and evaluation techniques for early design stage performance comparison. University of Michigan, USA, 1996 - 1995
- [c3]John-David Wellman, Edward S. Davidson:
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ICCD 1995: 110-115 - 1993
- [c2]Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson:
Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. International Conference on Supercomputing 1993: 240-250 - [c1]Pradip Bose, John-David Wellman:
MIPS-Driven Early Design and Analysis of VLSI CPU Chips. VLSI Design 1993: 256-259
Coauthor Index
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last updated on 2024-08-13 20:45 CEST by the dblp team
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